Intel IQ80321 manual Switches and Jumpers, Switch Summary

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Intel® IQ80321 I/O Processor Evaluation Platform

Hardware Reference Section

3.10Switches and Jumpers

3.10.1Switch Summary

Table 24.	Switch Summary

	Switch	Association	Description	Factory
	Switch	Association	Description	Default
				Default

	S7E1-1	-	Spare	Off

	S7E1-2	IOP	RST_MODE: Sets IOP Reset-Mode operation	Off

	S7E1-3	IOP	RETRY: Sets IOP RETRY-Mode operation	Offa
	S7E1-4	SPCI-X Bus	IDSEL_EN_PCIX1: Enables GPIO IDSEL control for the PCI-X slot	Off

	S7E1-5	SPCI-X Bus	IDSEL_EN_GBE: Enables GPIO IDSEL control for GBE NIC	Off

	S7E1-6	SPCI-X Clock	Set SPCI-X clock configuration	Off

	S7E1-7			On
	S7E1-7			On

	S7E1-8	SPCI-X Clock	Enables SPCI-X clock circuit enable	Off

	S8E1-1	-	Spare	Off

	S8E1-2	SPCI-X Bus	QSWITCHEN: Quick-Switch to make GbE NIC visible on the SPCI-X bus	On

	S8E1-3	PCI-X Bridge	S_INT_ARB_EN: Internal bridge arbiter operation	On

	S8E1-4	PCI-X Bridge	S_SEL100: SPCI-X max operation frequency indictor	Off

	S8E1-5	PCI-X Bridge	S_DRVR_MODE: Driver impedance selection for SPCI-X bus	On

	S8E1-6	PCI-X Bridge	P_DRVR_MODE: Driver impedance selection for PPCI-X bus	On

	S8E1-7	PCI-X Bridge	IDSEL_REROUTE_EN: Sets the value of SPCI-X private dev mask	Offa
	S8E1-8	PCI-X Bridge	OPAQUE-EN: controls OPAQUE memory register	Off

	S8E2-1	SPCI-X Bus	PCIXCAP: Force PCI-X capability for SPCI-X Bus	Off

	S8E2-2			On
	S8E2-2			On

	S8E2-3	-	Spare	Offb
	S8E2-4	SPCI-X Bus	M66EN: Forces the PCI 66 or 33 operation for SPCI-X Bus	Off

	S9E1-1	PCI-X Bridge	PCIXCAP: Set Primary PCI-X capability for the bridge	Off

	S9E1-2			Off
	S9E1-2			Off

	S9E1-3	-	Spare	On

	S9E1-4	PCI-X Bridge	M66EN: Forces the PCI 66 or 33 operation for the primary side	Off

	S1D1-1			Off

	S1D1-2	DDR Memory	SPD EEPROM: Configure serial EEPROM Address Range	Off

	S1D1-3			Off

	S1D1-4	-	Spare	Off

	S4D1-1	SPCI-X Bus	Selects Private/Public IDSEL routing for PCI-X expansion slot	Ona, c
	S4D1-2	SPCI-X Bus		Offa, c
	S4D1-2			Offa, c
	S4D1-3	SPCI-X Bus	Selects Private/Public IDSEL routing for GBE NIC	Ona, d
	S4D1-4	SPCI-X Bus	Selects Private/Public IDSEL routing for GBE NIC	Offa, d
	S4D1-4			Offa, d
	S1H2	Board Reset	Push-Button Reset – for debug use	Bounce

a.Use opposite settings when using an 80300-BP Backplane from Cyclone Micro Systems or most other PCI-X backplanes (switches S7E1-3, S8E1-7, S4D1-1, 2, 3, 4).

b.On FAB C boards S8E2-3 is not a spare and it must be turned on.

c.Switches S4D1-1 and 2 have to always be opposite of each other.

d.Switches S4D1-3 and 4 have to always be opposite of each other.

52	Board Manual

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Contents Intel IQ80321 I/O Processor Evaluation Platform Board ManualIntel IQ80321 I/O Processor Evaluation Platform Board ManualContents Debug Interface Dram 100 119 Figures Tables 105 Revision History DescriptionThis page intentionally left blank Document Purpose and Scope Related DocumentsElectronic Information Component ReferencesElectronic Information Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Block Diagram Intel 80321 I/O ProcessorIntel IQ80321 I/O Processor Evaluation Platform Summary of Features Intel IQ80321 Evaluation Platform Board FeaturesFeature Definition Kit Content Hardware InstallationFirst-Time Installation and Test Power and Backplane RequirementsFactory Settings Contents of the FlashDevelopment Strategy Supported Tool BucketsRedhat Redboot Target MonitorsARM Firmware Suite ARM Angel Semihosting File I/OSerial-UART Communication Host Communications ExamplesEthernet-Network Communication Jtag Debug Communication Jtag Debug CommunicationCommunicating with Redboot GNUPro GDB/InsightIntel IQ80321 I/O Processor Evaluation Platform Connecting with GDB GDB set remotebaudARM Extended Debugger This page intentionally left blank Functional Diagram IntelForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesBattery Backup DDR Memory FeaturesMemory Subsystem Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80321 I/O Processor Operation Mode Interrupt Routing 80321 I/O ProcessorPeripheral Bus Features Intel IQ80321 Evaluation Platform Board Peripheral BusFlash ROM Features Flash ROMUart Features UartHEX Display HEX Display on the Peripheral BusRotary Switch Rotary Switch RequirementsBattery Status Battery Status Buffer RequirementsDebug Interface Console Serial PortEthernet Port Intel 82544EI Gigabit Ethernet ControllerLogic-Analyzer Connectors Jtag Debug3.1 Jtag Port Jtag Port Pin-outMicor J3F2 Signal/Pins Mictor J3F2Schematic Signal Name Micor J2F1 Signal/PinsMictor J2F1 Micor J1C1 Signal/Pins Mictor J1C1Micor J3C1 Signal/Pins Mictor J3C1Micor J2C1 Signal/Pins Mictor J2C1Reset Requirements/Schemes Board Reset SchemeReset Sources Switches and Jumpers Switch SummaryPCI-X Bridge Initialization Signals User Defined SwitchesPcix Initialization Summary Default Switch Settings Visual Jumper Summary Connector SummaryGeneral Purpose Input/Output Header Secondary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeDetail Descriptions of Switches/Jumpers Switch S7E1- 2/3Switch S7E1- 4/5 Switch S7E1- 6/7Switch S7E1 Switch S7E1 8 DescriptionsSwitch S7E1 8 Settings and Operation Mode S7E1-8Switch S8E1 Switch S8E1 5 Descriptions Switch S8E1 5 Settings and Operation ModeSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 DescriptionsSwitch S8E1 7 Descriptions Switch S8E1 7 Settings and Operation ModeSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation ModeSwitch S8E2 1/2 Switch S8E2Switch S9E1 Switch S9E1 13 DescriptionsSwitch S9E1 13 Settings and Operation Mode Switch S9E1 4 DescriptionsSwitch S4D1 1/2 Switch S1D1 1/2Switch S4D1 3/4 Jumper J3E1 Jumper J1G2Jumper J3G1 Jumper J9E1 Jumper J9F1This page intentionally left blank Private Device Configuration Requirements Private Device ConfigurationIdsel Routing for Private Device Configuration Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private DeviceDram Components on the Peripheral BusDDR Memory Bias Voltage Minimum/Maximum Values Parameter VoltagesSoftware Reference Uart Register Settings Address Read Register Write RegisterHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80321 I/O Processor Memory Map Board Support Package BSP ExamplesIntel 80321 I/O Processor Memory Map Redboot* Intel IQ80321 Memory Map Physical Address Range DescriptionRedboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory MapRedboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory MapRedboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Purpose IntroductionNecessary Hardware and Software Related Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Displaying Source CodeUsing Breakpoints Setting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Watch Window Registers WindowVariables Window Debugging Basics Hardware and Software BreakpointsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping