Intel IQ80321 manual Board Manual 107

Page 107

Intel® IQ80321 I/O Processor Evaluation Platform

Getting Started and Debugger

C.2 Setup

C.2.1 Hardware Setup

Use Figure 28 and the rest of the Intel® IQ80321 Evaluation Platform Board Manual, to set up the hardware.

•Connect the Raven to the host via the parallel port and to the evaluation board via the 20-pin JTAG connector.

Note: The parallel port must be configured to EPP mode for the Macraigor Raven to work properly.

The parallel port setting can be changed in the BIOS setup program or in Control Panel. More information on the Raven can be found at the Macraigor web site. Test software for the Raven is free and available for download at: http://www.ocdemon.net/Merchant2/merchant.mv?Screen=CTGY&Store_Code=MTS&Category_C ode=pinouts.

•Connect a serial cable from the evaluation board to the host.

Note: The serial cable connects to the evaluation board with an RJ11 connector and connects to the host computer serial port via an RJ11 to DB9F adaptor. The serial port configuration is covered in the configuration section below.

•The IQ80321 plugs into a bus master PCI or PCI-X slot on the backplane or platform.

Note: There are many dip switches on the evaluation board which are used to configure the IBM bridge. Use the dip switch and jumper sections of the Intel® IQ80321 Evaluation Platform Board Manual, section

3.10.2to configure these switches. A work sheet is highly recommended when working out the switch settings, Since there are a large number of switches, a record of the settings and the reasons for their selection very useful. Check the system requirements of Microsoft Visual Studio and ATI CodeLab to make sure that the host is sufficient. The platform or backplane must have a 3.3 volt PCI-X or PCI slot. The evaluation board is not 5 volt tolerant and damage occurs when 5 volts are applied.

Figure 30. Intel® IQ80321 Hardware Setup Flow Chart

Host

Serial Cable

JTAG

Evaluation Board

Backplane or PCI-X Platform

Parallel Port Cable

20-Pin JTAG Connector

Board Manual

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Contents Board Manual Intel IQ80321 I/O Processor Evaluation PlatformBoard Manual Intel IQ80321 I/O Processor Evaluation PlatformContents Debug Interface Dram 100 119 Figures Tables 105 Description Revision HistoryThis page intentionally left blank Related Documents Document Purpose and ScopeComponent Reference Electronic InformationComponent References Electronic InformationDefinition Terms and DefinitionsTerms and Definitions Intel 80321 I/O Processor Intel 80321 I/O Processor Block DiagramIntel IQ80321 I/O Processor Evaluation Platform Feature Definition Intel IQ80321 Evaluation Platform Board FeaturesSummary of Features Power and Backplane Requirements Kit ContentHardware Installation First-Time Installation and TestSupported Tool Buckets Factory SettingsContents of the Flash Development StrategyTarget Monitors Redhat RedbootARM Firmware Suite Semihosting File I/O ARM AngelEthernet-Network Communication Host Communications ExamplesSerial-UART Communication Jtag Debug Communication Jtag Debug CommunicationGNUPro GDB/Insight Communicating with RedbootIntel IQ80321 I/O Processor Evaluation Platform GDB set remotebaud Connecting with GDBARM Extended Debugger This page intentionally left blank Intel Functional DiagramBoard Form-Factor/Connectivity Form-Factor/Connectivity FeaturesPower Features PowerSupported Dimm Types Battery BackupDDR Memory Features Memory SubsystemFlash Memory Requirements Flash Memory RequirementsIntel 80321 I/O Processor Operation Mode 80321 I/O Processor Interrupt RoutingIntel IQ80321 Evaluation Platform Board Peripheral Bus Peripheral Bus FeaturesFlash ROM Flash ROM FeaturesUart Uart FeaturesHEX Display on the Peripheral Bus HEX DisplayRotary Switch Requirements Rotary SwitchBattery Status Buffer Requirements Battery StatusIntel 82544EI Gigabit Ethernet Controller Debug InterfaceConsole Serial Port Ethernet PortJtag Port Pin-out Logic-Analyzer ConnectorsJtag Debug 3.1 Jtag PortMictor J3F2 Micor J3F2 Signal/PinsMictor J2F1 Micor J2F1 Signal/PinsSchematic Signal Name Mictor J1C1 Micor J1C1 Signal/PinsMictor J3C1 Micor J3C1 Signal/PinsMictor J2C1 Micor J2C1 Signal/PinsReset Sources Board Reset SchemeReset Requirements/Schemes Switch Summary Switches and JumpersPcix Initialization Summary User Defined SwitchesPCI-X Bridge Initialization Signals Default Switch Settings Visual General Purpose Input/Output Header Connector SummaryJumper Summary S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation Mode Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation SettingsSwitch S7E1- 2/3 Detail Descriptions of Switches/JumpersSwitch S7E1- 6/7 Switch S7E1- 4/5S7E1-8 Switch S7E1Switch S7E1 8 Descriptions Switch S7E1 8 Settings and Operation ModeSwitch S8E1 Switch S8E1 6 Descriptions Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 5 Driver Mode Output ImpedancesSwitch S8E1 8 Settings and Operation Mode Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 DescriptionsSwitch S8E2 Switch S8E2 1/2Switch S9E1 4 Descriptions Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 13 Settings and Operation ModeSwitch S4D1 3/4 Switch S1D1 1/2Switch S4D1 1/2 Jumper J3G1 Jumper J1G2Jumper J3E1 Jumper J9F1 Jumper J9E1This page intentionally left blank Idsel Routing for Private Device Configuration Private Device ConfigurationPrivate Device Configuration Requirements Interrupt Routing for Secondary PCI-X Private Device Interrupt Routing for Private Device ConfigurationParameter Voltages DramComponents on the Peripheral Bus DDR Memory Bias Voltage Minimum/Maximum ValuesSoftware Reference Address Read Register Write Register Uart Register SettingsHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80321 I/O Processor Memory Map Board Support Package BSP ExamplesIntel 80321 I/O Processor Memory Map Physical Address Range Description Redboot* Intel IQ80321 Memory MapRedboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80321 Physical Memory Map VisualRedboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80321 Virtual Memory Map VisualRedboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Necessary Hardware and Software IntroductionPurpose Related Web Sites Hardware Setup SetupSoftware Flow Diagram Software SetupCreating a New Project New Project SetupConfiguration Overview Flashing with JtagUsing Flash Programmer Building an Executable File From Example Code Debugging Out of FlashRunning the CodeLab Debugger Launching and Configuring DebuggerDisplaying Source Code Manually Loading and Executing an Application ProgramUsing Breakpoints Stepping Through the Code Setting CodeLab Debug OptionsExploring the CodeLab Debug Windows Variables Window Registers WindowWatch Window Hardware Breakpoints Debugging BasicsHardware and Software Breakpoints Software BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping