Intel IQ80321 manual 3 C.9.3 Exceptions/Trapping

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Intel® IQ80321 I/O Processor Evaluation Platform

Getting Started and Debugger

C.9.3 C.9.3 Exceptions/Trapping

A debug exception causes the processor to re-direct execution to a debug event handling routine. The Intel® 80200 processor debug architecture defines the following debug exceptions:

•instruction breakpoint

•data breakpoint

•software breakpoint

•external debug break

•exception vector trap

•trace-buffer full break

When a debug exception occurs, the processor actions depend on whether the debug unit is configured for Halt mode or Monitor mode.

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Contents Intel IQ80321 I/O Processor Evaluation Platform Board ManualIntel IQ80321 I/O Processor Evaluation Platform Board ManualContents Debug Interface Dram 100 119 Figures Tables 105 Revision History DescriptionThis page intentionally left blank Document Purpose and Scope Related DocumentsElectronic Information Component ReferencesElectronic Information Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Block Diagram Intel 80321 I/O ProcessorIntel IQ80321 I/O Processor Evaluation Platform Intel IQ80321 Evaluation Platform Board Features Summary of FeaturesFeature Definition Kit Content Hardware InstallationFirst-Time Installation and Test Power and Backplane RequirementsFactory Settings Contents of the FlashDevelopment Strategy Supported Tool BucketsRedhat Redboot Target MonitorsARM Firmware Suite ARM Angel Semihosting File I/OHost Communications Examples Serial-UART CommunicationEthernet-Network Communication Jtag Debug Communication Jtag Debug CommunicationCommunicating with Redboot GNUPro GDB/InsightIntel IQ80321 I/O Processor Evaluation Platform Connecting with GDB GDB set remotebaudARM Extended Debugger This page intentionally left blank Functional Diagram IntelForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesBattery Backup DDR Memory FeaturesMemory Subsystem Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80321 I/O Processor Operation Mode Interrupt Routing 80321 I/O ProcessorPeripheral Bus Features Intel IQ80321 Evaluation Platform Board Peripheral BusFlash ROM Features Flash ROMUart Features UartHEX Display HEX Display on the Peripheral BusRotary Switch Rotary Switch RequirementsBattery Status Battery Status Buffer RequirementsDebug Interface Console Serial PortEthernet Port Intel 82544EI Gigabit Ethernet ControllerLogic-Analyzer Connectors Jtag Debug3.1 Jtag Port Jtag Port Pin-outMicor J3F2 Signal/Pins Mictor J3F2Micor J2F1 Signal/Pins Schematic Signal NameMictor J2F1 Micor J1C1 Signal/Pins Mictor J1C1Micor J3C1 Signal/Pins Mictor J3C1Micor J2C1 Signal/Pins Mictor J2C1Board Reset Scheme Reset Requirements/SchemesReset Sources Switches and Jumpers Switch SummaryUser Defined Switches PCI-X Bridge Initialization SignalsPcix Initialization Summary Default Switch Settings Visual Connector Summary Jumper SummaryGeneral Purpose Input/Output Header Secondary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeDetail Descriptions of Switches/Jumpers Switch S7E1- 2/3Switch S7E1- 4/5 Switch S7E1- 6/7Switch S7E1 Switch S7E1 8 DescriptionsSwitch S7E1 8 Settings and Operation Mode S7E1-8Switch S8E1 Switch S8E1 5 Descriptions Switch S8E1 5 Settings and Operation ModeSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 DescriptionsSwitch S8E1 7 Descriptions Switch S8E1 7 Settings and Operation ModeSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation ModeSwitch S8E2 1/2 Switch S8E2Switch S9E1 Switch S9E1 13 DescriptionsSwitch S9E1 13 Settings and Operation Mode Switch S9E1 4 DescriptionsSwitch S1D1 1/2 Switch S4D1 1/2Switch S4D1 3/4 Jumper J1G2 Jumper J3E1Jumper J3G1 Jumper J9E1 Jumper J9F1This page intentionally left blank Private Device Configuration Private Device Configuration RequirementsIdsel Routing for Private Device Configuration Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private DeviceDram Components on the Peripheral BusDDR Memory Bias Voltage Minimum/Maximum Values Parameter VoltagesSoftware Reference Uart Register Settings Address Read Register Write RegisterHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Board Support Package BSP Examples Intel 80321 I/O Processor Memory MapIntel 80321 I/O Processor Memory Map Redboot* Intel IQ80321 Memory Map Physical Address Range DescriptionRedboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory MapRedboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory MapRedboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Introduction PurposeNecessary Hardware and Software Related Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Displaying Source CodeUsing Breakpoints Setting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Registers Window Watch WindowVariables Window Debugging Basics Hardware and Software BreakpointsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping