Intel IQ80321 manual Board Manual 105

Page 105

Intel® IQ80321 I/O Processor Evaluation Platform

Getting Started and Debugger

Getting Started and Debugger

C

C.1 Introduction

This appendix pertains to CodeLab version 2.3 and later which uses Microsoft's Visual Studio .NET. For CodeLab version 2.2 and earlier, refer to appendix B.

C.1.1 Purpose

The purpose of this appendix is to help the user setup and become familiar with the Intel ® IQ80321 Evaluation Platform Board (IQ80321) and, other related hardware and software. This appendix steps the user through an example program using:

CodeLab EDE

CodeLab EDE debugger

Macraigor* Raven* JTAG

This programming also includes:

 

 

 

software setup

compiling

linking

debugging example code

The user tours the major features of the debugger and explores some of the basics of debugging. By the end of this exercise, the user has been given a general understanding of the ATI* development tools and can begin working on new applications.

C.1.2 Necessary Hardware and Software

This example uses the ATI CodeLab plug-in for Microsoft* Visual Studio, the GNU* Pro compiler, the Macraigor Raven JTAG connector, and the IQ80321.

C.1.3

Related Documents

 

Table 92.

Related Documents

 

 

 

 

 

 

 

Document Title

Document #

 

 

 

Intel®

80321 I/O Processor Developer’s Manual

273517

Intel®

80200 Processor based on Intel® XScaleMicroarchitecture Developer’s Manual

273411

Intel®

IQ80321 Evaluation Platform Board Manual

273521

Hot-Debug for Intel® XScaleCore Debug White Paper

273539

ARM Assemblers Guide (http://www.arm.com/support/574FKU/$File/ADS_AssemblerGuide_B.pdf)

 

 

 

ADS Debug Target Guide (http://www.arm.com/support/574FWT/$File/ADS_DebugTargetGuide_D.pdf)

 

 

 

CodeLab Debug for ARMa

 

a.This document installs to C:\Ati\docs\codelab debug.pdf.

Many of these documents load as part of ATI CodeLab install (Start/Programs/ Accelerated Technology/Documentation). This menu contains both the ARM* ADS and CodeLab documents.

Board Manual

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Image 105
Contents Board Manual Intel IQ80321 I/O Processor Evaluation PlatformBoard Manual Intel IQ80321 I/O Processor Evaluation PlatformContents Debug Interface Dram 100 119 Figures Tables 105 Description Revision HistoryThis page intentionally left blank Related Documents Document Purpose and ScopeComponent References Electronic InformationElectronic Information Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Intel 80321 I/O Processor Block DiagramIntel IQ80321 I/O Processor Evaluation Platform Intel IQ80321 Evaluation Platform Board Features Summary of FeaturesFeature Definition Hardware Installation Kit ContentFirst-Time Installation and Test Power and Backplane RequirementsContents of the Flash Factory SettingsDevelopment Strategy Supported Tool BucketsTarget Monitors Redhat RedbootARM Firmware Suite Semihosting File I/O ARM AngelHost Communications Examples Serial-UART CommunicationEthernet-Network Communication Jtag Debug Communication Jtag Debug CommunicationGNUPro GDB/Insight Communicating with RedbootIntel IQ80321 I/O Processor Evaluation Platform GDB set remotebaud Connecting with GDBARM Extended Debugger This page intentionally left blank Intel Functional DiagramBoard Form-Factor/Connectivity Form-Factor/Connectivity FeaturesPower Features PowerDDR Memory Features Battery BackupMemory Subsystem Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80321 I/O Processor Operation Mode 80321 I/O Processor Interrupt RoutingIntel IQ80321 Evaluation Platform Board Peripheral Bus Peripheral Bus FeaturesFlash ROM Flash ROM FeaturesUart Uart FeaturesHEX Display on the Peripheral Bus HEX DisplayRotary Switch Requirements Rotary SwitchBattery Status Buffer Requirements Battery StatusConsole Serial Port Debug InterfaceEthernet Port Intel 82544EI Gigabit Ethernet ControllerJtag Debug Logic-Analyzer Connectors3.1 Jtag Port Jtag Port Pin-outMictor J3F2 Micor J3F2 Signal/PinsMicor J2F1 Signal/Pins Schematic Signal NameMictor J2F1 Mictor J1C1 Micor J1C1 Signal/PinsMictor J3C1 Micor J3C1 Signal/PinsMictor J2C1 Micor J2C1 Signal/PinsBoard Reset Scheme Reset Requirements/SchemesReset Sources Switch Summary Switches and JumpersUser Defined Switches PCI-X Bridge Initialization SignalsPcix Initialization Summary Default Switch Settings Visual Connector Summary Jumper SummaryGeneral Purpose Input/Output Header Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeSwitch S7E1- 2/3 Detail Descriptions of Switches/JumpersSwitch S7E1- 6/7 Switch S7E1- 4/5Switch S7E1 8 Descriptions Switch S7E1Switch S7E1 8 Settings and Operation Mode S7E1-8Switch S8E1 Switch S8E1 5 Settings and Operation Mode Switch S8E1 5 DescriptionsSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 7 DescriptionsSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation ModeSwitch S8E2 Switch S8E2 1/2Switch S9E1 13 Descriptions Switch S9E1Switch S9E1 13 Settings and Operation Mode Switch S9E1 4 DescriptionsSwitch S1D1 1/2 Switch S4D1 1/2Switch S4D1 3/4 Jumper J1G2 Jumper J3E1Jumper J3G1 Jumper J9F1 Jumper J9E1This page intentionally left blank Private Device Configuration Private Device Configuration RequirementsIdsel Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private Device Interrupt Routing for Private Device ConfigurationComponents on the Peripheral Bus DramDDR Memory Bias Voltage Minimum/Maximum Values Parameter VoltagesSoftware Reference Address Read Register Write Register Uart Register SettingsHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Board Support Package BSP Examples Intel 80321 I/O Processor Memory MapIntel 80321 I/O Processor Memory Map Physical Address Range Description Redboot* Intel IQ80321 Memory MapRedboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80321 Physical Memory Map VisualRedboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80321 Virtual Memory Map VisualRedboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Introduction PurposeNecessary Hardware and Software Related Web Sites Hardware Setup SetupSoftware Flow Diagram Software SetupCreating a New Project New Project SetupConfiguration Overview Flashing with JtagUsing Flash Programmer Building an Executable File From Example Code Debugging Out of FlashRunning the CodeLab Debugger Launching and Configuring DebuggerDisplaying Source Code Manually Loading and Executing an Application ProgramUsing Breakpoints Stepping Through the Code Setting CodeLab Debug OptionsExploring the CodeLab Debug Windows Registers Window Watch WindowVariables Window Hardware and Software Breakpoints Debugging BasicsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping