Intel IQ80321 manual Jumper Summary, Connector Summary, General Purpose Input/Output Header

Intel® IQ80321 I/O Processor Evaluation Platform

Hardware Reference Section

3.10.4Jumper Summary

Table 31.	Jumper Summary
	Jumper	Association	Description	Factory Default
	J1G2	PPCI-X Reset	Can isolated the PCI-X reset from getting to the board.	2-3
	J3E1	SPCI-X Clock	Enables spread-spectrum on the SPCI-X clock.	2-3
	J3G1	PCI-X Bridge	Enables Bridge access from the SPCI-X side.	2-3
	J9E1	PCI-X Bridge	Enables Base Address Register (BAR).	2-3
	J9F1	PCI-X Bridge	Allows user to control initialization sequence on the	2-3
			bridge.

3.10.5Connector Summary

Table 32.	Connector Summary
	Connector	Description
	J1F1	RJ45 Network Connector for GbE NIC
	J1G1	RJ11 Serial Port Connector for UART
	J7A1	20-Pin JTAG Debug Connector
	J1C1	Logic analyzer Mictor Connector for SPCI-X Bus
	J2C1	Logic analyzer Mictor Connector for SPCI-X Bus
	J3C1	Logic analyzer Mictor Connector for SPCI-X Bus
	J2F1	Logic analyzer Mictor Connector for Intel® 80321 I/O processor Peripheral Bus
	J3F2	Logic analyzer Mictor Connector for 80321 Peripheral Bus
	J3F1	General Purpose I/O (GPIO) Header – GPIO 0-2
	J1A1	Secondary PCI-X Expansion Slot
	J1B1	Secondary PCI-X Expansion Slot – Not Populated
	J2H1	Primary PCI/PCI-X Edge Connector
	J6G1	DDR DIMM Connector
	J8H1	Connector for Battery

3.10.6General Purpose Input/Output Header

The board has three programmable general-purpose I/O pins (GPIO 0-3 on the 80321). These pins are connected to a 6-pin, 2.54 mm (0.100") header (connector J3F1).

Table 33.	GPIO Header (J3F1) Definition
	Pin	Signal	Pin	Signal
	1	GPIO0	4	GND
	2	GPIO1	5	GND
	3	GPIO2	6	GND

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