Intel
IQ80321
manual
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Functional Diagram
Micor J3F2 Signal/Pins
Default Switch Settings Visual
Connecting with GDB
Private Device Configuration
Board Reset Scheme
Setup
Logic-Analyzer Connectors
Battery Status
Battery Backup
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Intel
®
IQ80321 I/O Processor Evaluation Platform
Getting Started
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30
Board Manual
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Contents
Intel IQ80321 I/O Processor Evaluation Platform
Board Manual
Intel IQ80321 I/O Processor Evaluation Platform
Board Manual
Contents
Debug Interface
Dram
100
119
Figures
Tables
105
Revision History
Description
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Document Purpose and Scope
Related Documents
Electronic Information
Electronic Information
Component References
Component Reference
Terms and Definitions
Terms and Definitions
Definition
Intel 80321 I/O Processor Block Diagram
Intel 80321 I/O Processor
Intel IQ80321 I/O Processor Evaluation Platform
Intel IQ80321 Evaluation Platform Board Features
Summary of Features
Feature Definition
First-Time Installation and Test
Kit Content
Hardware Installation
Power and Backplane Requirements
Development Strategy
Factory Settings
Contents of the Flash
Supported Tool Buckets
Redhat Redboot
Target Monitors
ARM Firmware Suite
ARM Angel
Semihosting File I/O
Host Communications Examples
Serial-UART Communication
Ethernet-Network Communication
Jtag Debug Communication
Jtag Debug Communication
Communicating with Redboot
GNUPro GDB/Insight
Intel IQ80321 I/O Processor Evaluation Platform
Connecting with GDB
GDB set remotebaud
ARM Extended Debugger
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Functional Diagram
Intel
Form-Factor/Connectivity Features
Board Form-Factor/Connectivity
Power
Power Features
Memory Subsystem
Battery Backup
DDR Memory Features
Supported Dimm Types
Flash Memory Requirements
Flash Memory Requirements
Intel 80321 I/O Processor Operation Mode
Interrupt Routing
80321 I/O Processor
Peripheral Bus Features
Intel IQ80321 Evaluation Platform Board Peripheral Bus
Flash ROM Features
Flash ROM
Uart Features
Uart
HEX Display
HEX Display on the Peripheral Bus
Rotary Switch
Rotary Switch Requirements
Battery Status
Battery Status Buffer Requirements
Ethernet Port
Debug Interface
Console Serial Port
Intel 82544EI Gigabit Ethernet Controller
3.1 Jtag Port
Logic-Analyzer Connectors
Jtag Debug
Jtag Port Pin-out
Micor J3F2 Signal/Pins
Mictor J3F2
Micor J2F1 Signal/Pins
Schematic Signal Name
Mictor J2F1
Micor J1C1 Signal/Pins
Mictor J1C1
Micor J3C1 Signal/Pins
Mictor J3C1
Micor J2C1 Signal/Pins
Mictor J2C1
Board Reset Scheme
Reset Requirements/Schemes
Reset Sources
Switches and Jumpers
Switch Summary
User Defined Switches
PCI-X Bridge Initialization Signals
Pcix Initialization Summary
Default Switch Settings Visual
Connector Summary
Jumper Summary
General Purpose Input/Output Header
Primary PCI/PCI-X Operation Settings
Secondary PCI/PCI-X Operation Settings
Primary PCI/PCI-X Operation Settings
S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation Mode
Detail Descriptions of Switches/Jumpers
Switch S7E1- 2/3
Switch S7E1- 4/5
Switch S7E1- 6/7
Switch S7E1 8 Settings and Operation Mode
Switch S7E1
Switch S7E1 8 Descriptions
S7E1-8
Switch S8E1
Switch S8E1 5 Driver Mode Output Impedances
Switch S8E1 5 Descriptions
Switch S8E1 5 Settings and Operation Mode
Switch S8E1 6 Descriptions
Switch S8E1 8 Descriptions
Switch S8E1 7 Descriptions
Switch S8E1 7 Settings and Operation Mode
Switch S8E1 8 Settings and Operation Mode
Switch S8E2 1/2
Switch S8E2
Switch S9E1 13 Settings and Operation Mode
Switch S9E1
Switch S9E1 13 Descriptions
Switch S9E1 4 Descriptions
Switch S1D1 1/2
Switch S4D1 1/2
Switch S4D1 3/4
Jumper J1G2
Jumper J3E1
Jumper J3G1
Jumper J9E1
Jumper J9F1
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Private Device Configuration
Private Device Configuration Requirements
Idsel Routing for Private Device Configuration
Interrupt Routing for Private Device Configuration
Interrupt Routing for Secondary PCI-X Private Device
DDR Memory Bias Voltage Minimum/Maximum Values
Dram
Components on the Peripheral Bus
Parameter Voltages
Software Reference
Uart Register Settings
Address Read Register Write Register
Hex Display Connection to Peripheral Bus
Register Bitmap 7-Segment Display LSB FE85 0000h Write Only
Ethernet
Board Support Package BSP Examples
Intel 80321 I/O Processor Memory Map
Intel 80321 I/O Processor Memory Map
Redboot* Intel IQ80321 Memory Map
Physical Address Range Description
Redboot Intel IQ80321 Physical Memory Map Visual
Redboot Intel IQ80310 Physical Memory Map
Redboot Intel IQ80321 Virtual Memory Map Visual
Redboot Intel IQ80310 Virtual Memory Map
Redboot Intel IQ80321 Files
Redboot Intel IQ80321 DDR Memory Initialization Sequence
Redboot Switching
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IQ80310 and IQ80321 Comparisons
IQ80310 and IQ80321 Comparisons
Introduction
Purpose
Necessary Hardware and Software
Related Web Sites
Setup
Hardware Setup
Software Setup
Software Flow Diagram
New Project Setup
Creating a New Project
Configuration
Flashing with Jtag
Overview
Using Flash Programmer
Debugging Out of Flash
Building an Executable File From Example Code
Launching and Configuring Debugger
Running the CodeLab Debugger
Manually Loading and Executing an Application Program
Displaying Source Code
Using Breakpoints
Setting CodeLab Debug Options
Stepping Through the Code
Exploring the CodeLab Debug Windows
Registers Window
Watch Window
Variables Window
Software Breakpoints
Debugging Basics
Hardware and Software Breakpoints
Hardware Breakpoints
Exceptions/Trapping
104
Board Manual 105
106
Board Manual 107
Flash Memory Evaluation Board 108
Board Manual 109
110
Board Manual 111
112
Board Manual 113
114
Board Manual 115
116
4 4 Debug and Console Windows
118
Board Manual 119
3 C.9.3 Exceptions/Trapping
Related pages
Where can I find the eHELP section for TV operations?
Find the eHELP section
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