Intel manual Redboot* Intel IQ80321 Memory Map, Physical Address Range Description

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Intel® IQ80321 I/O Processor Evaluation Platform

Software Reference

5.4.2Redboot* Intel® IQ80321 Memory Map

The virtual memory maps use a C, B, and X column to indicate the caching policy for the region.

X	C	B	Description

0	0	0	Un-cached/Un-buffered

0	0	1	Un-cached/Buffered

0	1	0	Cached/Buffered Write Through, Read Allocate

0	1	1	Cached/Buffered Write Back, Read Allocate

1	0	0	Invalid -- not used

1	0	1	Un-cached/Buffered No write buffer coalescing

1	1	0	Mini D-Cache - Policy set by Auxiliary Control Register

1	1	1	Cached/Buffered Write Back, Read/Write Allocate

Physical Address Range		Description

0x0000 0000 - 0x7FFF FFFF		ATU Outbound Direct Window

0x8000 0000 - 0x900F FFFF		ATU Outbound Translate Windows

0xa000 0000 - 0xBFFF FFFF		SDRAM

0xf000 0000 - 0xF080 0000		FLASH (PBIUa CS0b)
0xfe80 0000 - 0xFE80 0FFF		UART (PBIU CS1)

0xfe84 0000	- 0xFE84 0FFF	Left 7-segment LED (PBIU CS3)

0xfe85 0000	- 0xFE85 0FFF	Right 7-segment LED (PBIU CS2)

0xfe8d 0000	- 0xFE8D 0FFF	Rotary Switch (PBIU CS4)

0xfe8f 0000 - 0xFE8F 0FFF		Battery Status (PBIU CS5)

0xfff0 0000 - 0xFFFF FFFF		Intel® 80321 I/O Processor Memory Mapped Registers

a.PBIU: Intel® 80321 I/O processor Peripheral Bus Interface Unit.

b.CS: Chip-Select for the PBIU on Intel® 80321 I/O processor.

Default Virtual Map	X	C	B	Description

0x00000000 - 0x1fffffff	1	1	1	SDRAM

0x20000000 - 0x9fffffff	0	0	0	Outbound Direct Window

0xa0000000 - 0xb00fffff	0	0	0	Outbound Translate Windows

0xc0000000 - 0xdfffffff	0	0	0	Un-cached alias for SDRAM

0xe0000000 - 0xe00fffff	1	1	1	Cache flush region (no phys memory)

0xf0000000 - 0xf0800000	0	1	0	Flash (PBIU CS0)

0xfe800000 - 0xfe800fff	0	0	0	UART (PBIU CS1)

0xfe840000 - 0xfe840fff	0	0	0	Left 7-segment LED (PBIU CS3)

0xfe850000 - 0xfe850fff	0	0	0	Right 7-segment LED (PBIU CS2)

0xfe8d0000 - 0xfe8d0fff	0	0	0	Rotary Switch (PBIU CS4)

0xfe8f0000 - 0xfe8f0fff	0	0	0	Battery Status (PBIU CS5)

0xfff00000 - 0xffffffff	0	0	0	Intel® 80321 I/O processor Memory Mapped Registers

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Contents Intel IQ80321 I/O Processor Evaluation Platform Board ManualIntel IQ80321 I/O Processor Evaluation Platform Board ManualContents Debug Interface Dram 100 119 Figures Tables 105 Revision History DescriptionThis page intentionally left blank Document Purpose and Scope Related DocumentsElectronic Information Electronic InformationComponent References Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Block Diagram Intel 80321 I/O ProcessorIntel IQ80321 I/O Processor Evaluation Platform Intel IQ80321 Evaluation Platform Board Features Summary of FeaturesFeature Definition First-Time Installation and Test Kit ContentHardware Installation Power and Backplane RequirementsDevelopment Strategy Factory SettingsContents of the Flash Supported Tool BucketsRedhat Redboot Target MonitorsARM Firmware Suite ARM Angel Semihosting File I/OHost Communications Examples Serial-UART CommunicationEthernet-Network Communication Jtag Debug Communication Jtag Debug CommunicationCommunicating with Redboot GNUPro GDB/InsightIntel IQ80321 I/O Processor Evaluation Platform Connecting with GDB GDB set remotebaudARM Extended Debugger This page intentionally left blank Functional Diagram IntelForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesMemory Subsystem Battery BackupDDR Memory Features Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80321 I/O Processor Operation Mode Interrupt Routing 80321 I/O ProcessorPeripheral Bus Features Intel IQ80321 Evaluation Platform Board Peripheral BusFlash ROM Features Flash ROMUart Features UartHEX Display HEX Display on the Peripheral BusRotary Switch Rotary Switch RequirementsBattery Status Battery Status Buffer RequirementsEthernet Port Debug InterfaceConsole Serial Port Intel 82544EI Gigabit Ethernet Controller3.1 Jtag Port Logic-Analyzer ConnectorsJtag Debug Jtag Port Pin-outMicor J3F2 Signal/Pins Mictor J3F2Micor J2F1 Signal/Pins Schematic Signal NameMictor J2F1 Micor J1C1 Signal/Pins Mictor J1C1Micor J3C1 Signal/Pins Mictor J3C1Micor J2C1 Signal/Pins Mictor J2C1Board Reset Scheme Reset Requirements/SchemesReset Sources Switches and Jumpers Switch SummaryUser Defined Switches PCI-X Bridge Initialization SignalsPcix Initialization Summary Default Switch Settings Visual Connector Summary Jumper SummaryGeneral Purpose Input/Output Header Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeDetail Descriptions of Switches/Jumpers Switch S7E1- 2/3Switch S7E1- 4/5 Switch S7E1- 6/7Switch S7E1 8 Settings and Operation Mode Switch S7E1Switch S7E1 8 Descriptions S7E1-8Switch S8E1 Switch S8E1 5 Driver Mode Output Impedances Switch S8E1 5 DescriptionsSwitch S8E1 5 Settings and Operation Mode Switch S8E1 6 DescriptionsSwitch S8E1 8 Descriptions Switch S8E1 7 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 8 Settings and Operation ModeSwitch S8E2 1/2 Switch S8E2Switch S9E1 13 Settings and Operation Mode Switch S9E1Switch S9E1 13 Descriptions Switch S9E1 4 DescriptionsSwitch S1D1 1/2 Switch S4D1 1/2Switch S4D1 3/4 Jumper J1G2 Jumper J3E1Jumper J3G1 Jumper J9E1 Jumper J9F1This page intentionally left blank Private Device Configuration Private Device Configuration RequirementsIdsel Routing for Private Device Configuration Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private DeviceDDR Memory Bias Voltage Minimum/Maximum Values DramComponents on the Peripheral Bus Parameter VoltagesSoftware Reference Uart Register Settings Address Read Register Write RegisterHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Board Support Package BSP Examples Intel 80321 I/O Processor Memory MapIntel 80321 I/O Processor Memory Map Redboot* Intel IQ80321 Memory Map Physical Address Range DescriptionRedboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory MapRedboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory MapRedboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Introduction PurposeNecessary Hardware and Software Related Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Displaying Source CodeUsing Breakpoints Setting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Registers Window Watch WindowVariables Window Software Breakpoints Debugging BasicsHardware and Software Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping