Intel IQ80321 manual Switch S8E1

Page 60

Intel® IQ80321 I/O Processor Evaluation Platform

Hardware Reference Section

3.10.9.5Switch S8E1- 2

Turn On to enable on-board Gigabit Ethernet, otherwise Off for better PCI-X loading/performance.

Table 47.

Switch S8E1 - 2: Descriptions

 

 

 

 

 

 

 

Switch

Association

Description

Factory Default

 

 

 

 

 

 

S8E1-2

SPCI-X Bus

QSWITCHEN: Quick-Switch to make GbE NIC visible

On

 

on the SPCI-X bus.

 

 

 

 

 

 

 

 

 

Table 48.

Switch S8E1 - 2: Settings and Operation Mode

 

S8E1-2

Operation Mode

 

 

 

 

Off

82544EI Isolated from secondary PCI-X bus.

 

 

 

 

On

82544EI Included on as a device on the secondary PCI-X bus.

 

 

 

3.10.9.6Switch S8E1- 3

Close to enable bridge to be the arbiter.

Table 49.

Switch S8E1 - 3: Descriptions

 

 

 

 

 

 

 

Switch

Association

Description

Factory Default

 

 

 

 

 

 

S8E1-3

PCI-X Bridge

S_INT_ARB_EN: Internal bridge arbiter operation.

On

 

 

 

 

 

Table 50.

Switch S8E1 - 3: Settings and Operation Mode

 

 

 

 

 

 

 

S8E1-3

 

Operation Mode

 

 

 

 

 

 

Off

Disable internal bridge arbiter, use external arbiter.

 

 

 

 

 

 

On

Use internal arbiter.

 

 

 

 

 

 

3.10.9.7Switch S8E1- 4

Used to choose between 100 MHz and 133 MHz maximum operating frequency on the secondary interface when in the PCI-X mode. It has no meaning in the PCI mode.

When the bridge initially samples a b’1’ value on the S_PCIXCAP input, then all clients on the bus are capable of PCI-X 133 operation. The bridge then samples the S_SEL100 input to distinguish between the 66-100 MHz and the 100-133 MHz clock frequency ranges. When it detects a b’1’ value on the S_SEL100 input, the bus is initialized with the PCI-X 100 initialization pattern. When the value is b’0’, the PCI-X 133 initialization pattern is used. These two ranges allow adjustment of the clock frequency to account for bus loading conditions.

Since the internal PLL is bypassed in the PCI mode and the S_CLK input is used directly, the IBM 133 PCI-X Bridge R2.0 has no need to distinguish between the PCI 66 and PCI 33 modes. Therefore the bridge does not have an I/O pin for the M66EN signal on its secondary interface.

Table 51.

Switch S8E1 - 4: Descriptions

 

 

 

 

 

 

 

Switch

Association

Description

Factory Default

 

 

 

 

 

 

S8E1-4

PCI-X Bridge

S_SEL100: SPCI-X max operation frequency indictor.

Off

 

 

 

 

 

Table 52.

Switch S8E1 - 4: Settings and Operation Mode

 

 

 

 

 

 

 

S8E1-4

 

Operation Mode

 

 

 

 

 

 

 

Off

1: 100 MHz.

 

 

 

 

 

 

 

 

On

0: 133 MHz.

 

 

 

 

 

 

 

60

Board Manual

Image 60
Contents Intel IQ80321 I/O Processor Evaluation Platform Board ManualIntel IQ80321 I/O Processor Evaluation Platform Board ManualContents Debug Interface Dram 100 119 Figures Tables 105 Revision History DescriptionThis page intentionally left blank Document Purpose and Scope Related DocumentsElectronic Information Component ReferencesElectronic Information Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Block Diagram Intel 80321 I/O ProcessorIntel IQ80321 I/O Processor Evaluation Platform Intel IQ80321 Evaluation Platform Board Features Summary of FeaturesFeature Definition Kit Content Hardware InstallationFirst-Time Installation and Test Power and Backplane RequirementsFactory Settings Contents of the FlashDevelopment Strategy Supported Tool BucketsRedhat Redboot Target MonitorsARM Firmware Suite ARM Angel Semihosting File I/OHost Communications Examples Serial-UART CommunicationEthernet-Network Communication Jtag Debug Communication Jtag Debug CommunicationCommunicating with Redboot GNUPro GDB/InsightIntel IQ80321 I/O Processor Evaluation Platform Connecting with GDB GDB set remotebaudARM Extended Debugger This page intentionally left blank Functional Diagram IntelForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesBattery Backup DDR Memory FeaturesMemory Subsystem Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80321 I/O Processor Operation Mode Interrupt Routing 80321 I/O ProcessorPeripheral Bus Features Intel IQ80321 Evaluation Platform Board Peripheral BusFlash ROM Features Flash ROMUart Features UartHEX Display HEX Display on the Peripheral BusRotary Switch Rotary Switch RequirementsBattery Status Battery Status Buffer RequirementsDebug Interface Console Serial PortEthernet Port Intel 82544EI Gigabit Ethernet ControllerLogic-Analyzer Connectors Jtag Debug3.1 Jtag Port Jtag Port Pin-outMicor J3F2 Signal/Pins Mictor J3F2Micor J2F1 Signal/Pins Schematic Signal NameMictor J2F1 Micor J1C1 Signal/Pins Mictor J1C1Micor J3C1 Signal/Pins Mictor J3C1Micor J2C1 Signal/Pins Mictor J2C1Board Reset Scheme Reset Requirements/SchemesReset Sources Switches and Jumpers Switch SummaryUser Defined Switches PCI-X Bridge Initialization SignalsPcix Initialization Summary Default Switch Settings Visual Connector Summary Jumper SummaryGeneral Purpose Input/Output Header Secondary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeDetail Descriptions of Switches/Jumpers Switch S7E1- 2/3Switch S7E1- 4/5 Switch S7E1- 6/7Switch S7E1 Switch S7E1 8 DescriptionsSwitch S7E1 8 Settings and Operation Mode S7E1-8Switch S8E1 Switch S8E1 5 Descriptions Switch S8E1 5 Settings and Operation ModeSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 DescriptionsSwitch S8E1 7 Descriptions Switch S8E1 7 Settings and Operation ModeSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation ModeSwitch S8E2 1/2 Switch S8E2Switch S9E1 Switch S9E1 13 DescriptionsSwitch S9E1 13 Settings and Operation Mode Switch S9E1 4 DescriptionsSwitch S1D1 1/2 Switch S4D1 1/2Switch S4D1 3/4 Jumper J1G2 Jumper J3E1Jumper J3G1 Jumper J9E1 Jumper J9F1This page intentionally left blank Private Device Configuration Private Device Configuration RequirementsIdsel Routing for Private Device Configuration Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private DeviceDram Components on the Peripheral BusDDR Memory Bias Voltage Minimum/Maximum Values Parameter VoltagesSoftware Reference Uart Register Settings Address Read Register Write RegisterHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Board Support Package BSP Examples Intel 80321 I/O Processor Memory MapIntel 80321 I/O Processor Memory Map Redboot* Intel IQ80321 Memory Map Physical Address Range DescriptionRedboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory MapRedboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory MapRedboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Introduction PurposeNecessary Hardware and Software Related Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Displaying Source CodeUsing Breakpoints Setting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Registers Window Watch WindowVariables Window Debugging Basics Hardware and Software BreakpointsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping