Intel manual Intel IQ80321 I/O Processor Evaluation Platform

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Intel® IQ80321 I/O Processor Evaluation Platform

Introduction

It is an integrated processor that addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs.

The PCI Bus is an industry standard, high performance low latency system bus. The 80321 PCI Bus is capable of 133 MHz operation in PCI-X mode as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. Also, the processor supports a 66 MHz conventional PCI mode as defined by the PCI Local Bus Specification, Revision 2.2. The addition of the Intel® XScale™ core brings intelligence to the PCI bus application bridge.

The 80321 is a single function PCI device. This function represents the address translation unit. The address translation unit is an “application bridge” as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. The 80321 contains PCI configuration space accessible through the PCI bus.

80321 core is based upon the Intel® XScale™ core. The core processor operates at a maximum frequency of 600 MHz. The instruction cache is 32 Kbytes (KB) in size and is 32-way set associative. Also, the core processor includes a data cache that is 32 KB and is 32-way set associative and a mini data cache that is 2 KB and is 2-way set associative.

The 80321 includes eight General Purpose I/O (GPIO) pins.

Board Manual

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Contents Board Manual Intel IQ80321 I/O Processor Evaluation PlatformBoard Manual Intel IQ80321 I/O Processor Evaluation PlatformContents Debug Interface Dram 100 119 Figures Tables 105 Description Revision HistoryThis page intentionally left blank Related Documents Document Purpose and ScopeComponent References Electronic InformationElectronic Information Component ReferenceDefinition Terms and DefinitionsTerms and Definitions Intel 80321 I/O Processor Intel 80321 I/O Processor Block DiagramIntel IQ80321 I/O Processor Evaluation Platform Feature Definition Intel IQ80321 Evaluation Platform Board FeaturesSummary of Features Hardware Installation Kit ContentFirst-Time Installation and Test Power and Backplane RequirementsContents of the Flash Factory SettingsDevelopment Strategy Supported Tool BucketsTarget Monitors Redhat RedbootARM Firmware Suite Semihosting File I/O ARM AngelEthernet-Network Communication Host Communications ExamplesSerial-UART Communication Jtag Debug Communication Jtag Debug CommunicationGNUPro GDB/Insight Communicating with RedbootIntel IQ80321 I/O Processor Evaluation Platform GDB set remotebaud Connecting with GDBARM Extended Debugger This page intentionally left blank Intel Functional DiagramBoard Form-Factor/Connectivity Form-Factor/Connectivity FeaturesPower Features PowerDDR Memory Features Battery BackupMemory Subsystem Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80321 I/O Processor Operation Mode 80321 I/O Processor Interrupt RoutingIntel IQ80321 Evaluation Platform Board Peripheral Bus Peripheral Bus FeaturesFlash ROM Flash ROM FeaturesUart Uart FeaturesHEX Display on the Peripheral Bus HEX DisplayRotary Switch Requirements Rotary SwitchBattery Status Buffer Requirements Battery StatusConsole Serial Port Debug InterfaceEthernet Port Intel 82544EI Gigabit Ethernet ControllerJtag Debug Logic-Analyzer Connectors3.1 Jtag Port Jtag Port Pin-outMictor J3F2 Micor J3F2 Signal/PinsMictor J2F1 Micor J2F1 Signal/PinsSchematic Signal Name Mictor J1C1 Micor J1C1 Signal/PinsMictor J3C1 Micor J3C1 Signal/PinsMictor J2C1 Micor J2C1 Signal/PinsReset Sources Board Reset SchemeReset Requirements/Schemes Switch Summary Switches and JumpersPcix Initialization Summary User Defined SwitchesPCI-X Bridge Initialization Signals Default Switch Settings Visual General Purpose Input/Output Header Connector SummaryJumper Summary Primary PCI/PCI-X Operation Settings Secondary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeSwitch S7E1- 2/3 Detail Descriptions of Switches/JumpersSwitch S7E1- 6/7 Switch S7E1- 4/5Switch S7E1 8 Descriptions Switch S7E1Switch S7E1 8 Settings and Operation Mode S7E1-8Switch S8E1 Switch S8E1 5 Settings and Operation Mode Switch S8E1 5 DescriptionsSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 DescriptionsSwitch S8E1 7 Settings and Operation Mode Switch S8E1 7 DescriptionsSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation ModeSwitch S8E2 Switch S8E2 1/2Switch S9E1 13 Descriptions Switch S9E1Switch S9E1 13 Settings and Operation Mode Switch S9E1 4 DescriptionsSwitch S4D1 3/4 Switch S1D1 1/2Switch S4D1 1/2 Jumper J3G1 Jumper J1G2Jumper J3E1 Jumper J9F1 Jumper J9E1This page intentionally left blank Idsel Routing for Private Device Configuration Private Device ConfigurationPrivate Device Configuration Requirements Interrupt Routing for Secondary PCI-X Private Device Interrupt Routing for Private Device ConfigurationComponents on the Peripheral Bus DramDDR Memory Bias Voltage Minimum/Maximum Values Parameter VoltagesSoftware Reference Address Read Register Write Register Uart Register SettingsHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80321 I/O Processor Memory Map Board Support Package BSP ExamplesIntel 80321 I/O Processor Memory Map Physical Address Range Description Redboot* Intel IQ80321 Memory MapRedboot Intel IQ80310 Physical Memory Map Redboot Intel IQ80321 Physical Memory Map VisualRedboot Intel IQ80310 Virtual Memory Map Redboot Intel IQ80321 Virtual Memory Map VisualRedboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Necessary Hardware and Software IntroductionPurpose Related Web Sites Hardware Setup SetupSoftware Flow Diagram Software SetupCreating a New Project New Project SetupConfiguration Overview Flashing with JtagUsing Flash Programmer Building an Executable File From Example Code Debugging Out of FlashRunning the CodeLab Debugger Launching and Configuring DebuggerDisplaying Source Code Manually Loading and Executing an Application ProgramUsing Breakpoints Stepping Through the Code Setting CodeLab Debug OptionsExploring the CodeLab Debug Windows Variables Window Registers WindowWatch Window Hardware and Software Breakpoints Debugging BasicsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping