Intel IQ80321 manual 112

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Intel® IQ80321 I/O Processor Evaluation Platform

Getting Started and Debugger

C.4.2 Using Flash Programmer

Note: The parallel port must be set to EPP mode or the Macraigor Raven will not work properly.

Download the RedBoot executable files from the following location: http://developer.intel.com/design/intelxscale/dev_tools/020523/RedBoot Debug Monitor for the Intel® IQ80310/IQ80321 boards

1.Double click on the “CodeLab Debug” icon on the desktop. The Connection Window appears.

2.Select Macraigor JTAG Connect a. Click Setup.

3.Select “ARM XScale”, correct LPT port, and “Raven” (do not press OK).

4.Click Additional Options…, check Enable Option, then press Configure The Console Options windows now appears.

5.Console Port: (Set appropriately)

Baud Rate: 115200

Data Bits: 8

Parity: None

Stop Bits: 1

Then Press OK, OK, OK (this returns to the Connect window).

6.Now press Connect. Assembly code now visible.

7.Select “Memory/Flash…”

The OCDemon Flash Memory Programmer window appears.

8.The Flash programmer needs a file which is architecture specific, in this case. In the Flash programmer window, select “File/Open”, then choose the file “XscaleVerde.ocd” at:

“C:\MGC\Embedded\codelab\codelab Debug\Macraigor\”.

9.Click the Program button.

10.Click Browse and “Files of type:” All Files, then choose the “redboot_ROM.srec” file (downloaded and uncompressed from developer.com).

11.Check box “Erase Target Flash Sector(s) Before Programming”.

12.Click Program.

The Flash now programs and verifies; click Close when 100% complete.

13.Cycle power to the board to see that the LEDs on the board sequence “8.8.”, “A5”, “A6”, “S.L”, then “A1”.

This is the normal LED sequence of RedBoot. The board may need to be reset more than once. Explore the other features of the Flash programming window. The contents of the Flash can be erased, copied to a file on the host, and verified against a file on the host.

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Contents Intel IQ80321 I/O Processor Evaluation Platform Board ManualIntel IQ80321 I/O Processor Evaluation Platform Board ManualContents Debug Interface Dram 100 119 Figures Tables 105 Revision History DescriptionThis page intentionally left blank Document Purpose and Scope Related DocumentsElectronic Information Component ReferencesElectronic Information Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80321 I/O Processor Block Diagram Intel 80321 I/O ProcessorIntel IQ80321 I/O Processor Evaluation Platform Summary of Features Intel IQ80321 Evaluation Platform Board FeaturesFeature Definition Kit Content Hardware InstallationFirst-Time Installation and Test Power and Backplane RequirementsFactory Settings Contents of the FlashDevelopment Strategy Supported Tool BucketsRedhat Redboot Target MonitorsARM Firmware Suite ARM Angel Semihosting File I/OSerial-UART Communication Host Communications ExamplesEthernet-Network Communication Jtag Debug Communication Jtag Debug CommunicationCommunicating with Redboot GNUPro GDB/InsightIntel IQ80321 I/O Processor Evaluation Platform Connecting with GDB GDB set remotebaudARM Extended Debugger This page intentionally left blank Functional Diagram IntelForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesBattery Backup DDR Memory FeaturesMemory Subsystem Supported Dimm TypesFlash Memory Requirements Flash Memory RequirementsIntel 80321 I/O Processor Operation Mode Interrupt Routing 80321 I/O ProcessorPeripheral Bus Features Intel IQ80321 Evaluation Platform Board Peripheral BusFlash ROM Features Flash ROMUart Features UartHEX Display HEX Display on the Peripheral BusRotary Switch Rotary Switch RequirementsBattery Status Battery Status Buffer RequirementsDebug Interface Console Serial PortEthernet Port Intel 82544EI Gigabit Ethernet ControllerLogic-Analyzer Connectors Jtag Debug3.1 Jtag Port Jtag Port Pin-outMicor J3F2 Signal/Pins Mictor J3F2Schematic Signal Name Micor J2F1 Signal/PinsMictor J2F1 Micor J1C1 Signal/Pins Mictor J1C1Micor J3C1 Signal/Pins Mictor J3C1Micor J2C1 Signal/Pins Mictor J2C1Reset Requirements/Schemes Board Reset SchemeReset Sources Switches and Jumpers Switch SummaryPCI-X Bridge Initialization Signals User Defined SwitchesPcix Initialization Summary Default Switch Settings Visual Jumper Summary Connector SummaryGeneral Purpose Input/Output Header Secondary PCI/PCI-X Operation Settings Primary PCI/PCI-X Operation SettingsPrimary PCI/PCI-X Operation Settings S9E1-1 S9E1-2 S9E1-3 S9E1-4 S8E1-6 Operation ModeDetail Descriptions of Switches/Jumpers Switch S7E1- 2/3Switch S7E1- 4/5 Switch S7E1- 6/7Switch S7E1 Switch S7E1 8 DescriptionsSwitch S7E1 8 Settings and Operation Mode S7E1-8Switch S8E1 Switch S8E1 5 Descriptions Switch S8E1 5 Settings and Operation ModeSwitch S8E1 5 Driver Mode Output Impedances Switch S8E1 6 DescriptionsSwitch S8E1 7 Descriptions Switch S8E1 7 Settings and Operation ModeSwitch S8E1 8 Descriptions Switch S8E1 8 Settings and Operation ModeSwitch S8E2 1/2 Switch S8E2Switch S9E1 Switch S9E1 13 DescriptionsSwitch S9E1 13 Settings and Operation Mode Switch S9E1 4 DescriptionsSwitch S4D1 1/2 Switch S1D1 1/2Switch S4D1 3/4 Jumper J3E1 Jumper J1G2Jumper J3G1 Jumper J9E1 Jumper J9F1This page intentionally left blank Private Device Configuration Requirements Private Device ConfigurationIdsel Routing for Private Device Configuration Interrupt Routing for Private Device Configuration Interrupt Routing for Secondary PCI-X Private DeviceDram Components on the Peripheral BusDDR Memory Bias Voltage Minimum/Maximum Values Parameter VoltagesSoftware Reference Uart Register Settings Address Read Register Write RegisterHex Display Connection to Peripheral Bus Register Bitmap 7-Segment Display LSB FE85 0000h Write Only Ethernet Intel 80321 I/O Processor Memory Map Board Support Package BSP ExamplesIntel 80321 I/O Processor Memory Map Redboot* Intel IQ80321 Memory Map Physical Address Range DescriptionRedboot Intel IQ80321 Physical Memory Map Visual Redboot Intel IQ80310 Physical Memory MapRedboot Intel IQ80321 Virtual Memory Map Visual Redboot Intel IQ80310 Virtual Memory MapRedboot Intel IQ80321 Files Redboot Intel IQ80321 DDR Memory Initialization Sequence Redboot Switching This page intentionally left blank IQ80310 and IQ80321 Comparisons IQ80310 and IQ80321 Comparisons Purpose IntroductionNecessary Hardware and Software Related Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeLaunching and Configuring Debugger Running the CodeLab DebuggerManually Loading and Executing an Application Program Displaying Source CodeUsing Breakpoints Setting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Watch Window Registers WindowVariables Window Debugging Basics Hardware and Software BreakpointsSoftware Breakpoints Hardware BreakpointsExceptions/Trapping 104 Board Manual 105 106 Board Manual 107 Flash Memory Evaluation Board 108 Board Manual 109 110 Board Manual 111 112 Board Manual 113 114 Board Manual 115 116 4 4 Debug and Console Windows 118 Board Manual 119 3 C.9.3 Exceptions/Trapping