Intel PXA27X manual Intel PXA27x Processor Low Power Operating Modes

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Intel® PXA27x Processor Family Power Requirements

3.0Intel® PXA27x Processor Low Power Operating Modes

The PXA27x processor provides several low-power operating modes that temporarily suspend or power down the core or peripherals to reduce power consumption. The external power supplies are disabled in some modes. Transitions between certain domains require a sequence of events and handshakes between the PXA27x processor and the external power management integrated circuit (PMIC) that are detailed in this section.

The PXA27x processor supports six operating modes, shown in Table 7.

Table 7. Intel® PXA27x Processor Operating Modes

Operating Modes

Description

 

 

Normal mode

All external power supplies are enabled and all internal domains are powered. The CPU

(Run/Turbo mode)

core and peripherals are fully functional.

 

 

Idle mode

The clocks to the CPU are disabled but context is retained. The peripherals continue

 

normal operation. All power supplies are enabled. An interrupt assertion causes the

 

transition back to normal mode.

 

 

Deep Idle mode

The core frequency is at 13 MHz (CCCR[CDPIS] is set) and the processor is in idle

 

mode.

 

 

Standby mode

The clocks to the CPU are disabled and the CPU is placed in a low leakage state but

 

context is retained. All external power supplies are enabled. Each internal SRAM bank

 

can be independently placed in a low-power mode where the state is retained but no

 

activity is allowed under program control. The PLLs are disabled and peripheral

 

operation is suspended. An interrupt assertion causes the transition back to normal

 

mode.

 

 

Sleep mode

All internal power domains except VCC_RTC and VCC_OSC are optionally powered

 

down. All clock sources except the real-time clock (RTC) and power manager are

 

disabled, and all external low-voltage power supplies (VCC_CORE, VCC_PLL, and

 

VCC_SRAM) controlled by PWR_EN are disabled. Recovery is initiated by external

 

wake-up events or select internal wake-up events. A system reboot is required because

 

the program counter is invalid.

 

 

Deep sleep mode

All internal power domains except VCC_RTC and VCC_OSC are powered down. All

 

clock sources except the real-time clock (RTC) and power manager are disabled, and the

 

external low-voltage supplies (VCC_CORE, VCC_PLL, and VCC_SRAM) controlled by

 

PWR_EN are disabled. The high-voltage power supplies (VCC_IO, VCC_MEM,

 

VCC_LCD, VCC_BB and VCC_USIM) controlled by SYS_EN are disabled. The active

 

internal power domains are powered from one of three internal regulators driven from the

 

backup battery signal, VCC_BATT. Recovery is initiated by external or select internal

 

wake-up events and requires a system reboot, because the program counter is invalid.

 

 

NOTE: Refer to the Intel® PXA27x Processor Family Developers Manual, “Clocks and Power” section for more information on low power modes

The state diagram in Figure 3 shows the transitions between operating modes and the events and conditions that cause or enable transitions.

Application Note

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Contents Application Note Intel PXA27x Processor Family Power RequirementsApplication Note Contents Figures Naming Conventions IntroductionPower Domain Enable1 Units Specified Levels Tolerance Volts Intel PXA27x Processor Power Supply DomainsExternal Power Supply Descriptions Pxtal PLLSram DMAIntel PXA27x Processor Power Supplies Power Domains and System Voltage/Current RequirementsVoltage Description Intel PXA27x Processor Voltage Domains Sheet 1Intel PXA27x Processor Voltage Domains Sheet 2 Power Supply Configuration in a Minimal SystemRegulators Required to Power the Intel PXA27x Processor Modeling Intel PXA27x processor power consumptionIntel PXA27x Processor Vcccore Supply Current Regulator DescriptionIntel PXA27x Processor Vcccore Supply Current Supply Current For Each Power DomainFrequency Dhrystones Power MPEG4 Decode Power Stress Intel PXA27x Processor Supply Current For Each Power Domain Default Reset ValuesName Functional Units Current mA @ Power VccbattBatteries Main BatteryBackup Battery Backup Battery Description Battery Chargers and Main PowerPossible Backup Battery Configurations Typical Battery and External Regulator Configuration Intel PXA27x Processor Operating Modes Intel PXA27x Processor Low Power Operating ModesCPDIS=0 Power Controller Interface SignalsCPDIS=1 System Power Enable Sysen / GPIO2 Power Enable PwrenPower Manager I2C Clock Pwrscl / GPIO3 Power Controller Interface SignalsOn, Off, and Reset Power Manager I2C Data Pwrsda / GPIO4User-Initiated Hard Reset Input System-Level Considerations for I2CUniversal Subscriber Identity Module Usim Power Manager Capacitor SignalsNRESET Output from Pmic to the Intel PXA27x Processor Cold-Start Power-On and Hardware Reset Power Mode SequencingPower-On Vcccore Vccpll Vccsram Initial Power Up and Deep Sleep Exit SequenceHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Pwrdel SysdelSleep Entry and Exit Sleep and Deep SleepDeep Sleep Entry and Exit Vcccore Regulator and Dynamic Voltage Management Dynamic Voltage Management DVMIntel PXA27x Processor Voltage Manager Power Manager I2C Interface Fault ManagementNVDDFAULT DVM SequencingGeneral Pmic Characteristics Power Management Integrated Circuit RequirementsNBATTFAULT Characteristic Description Features of a PmicGeneral Pmic Characteristics DVM Control Register Programmable Voltage ControlDVM Control and Status Register Other Aspects of an Integrated Power ControllerSummary Intel PXA27x Processor Family Power Requirements
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