Intel PXA27X manual Universal Subscriber Identity Module Usim, Power Manager Capacitor Signals

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Intel® PXA27x Processor Family Power Requirements

assertion of nRESET for a minimum of 50 ms. This type of reset would be used only for a severe and otherwise unrecoverable hardware or software problem, because it completely resets the state of the processor and may result in lost data. Refer to the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for the hardware reset timing specification.

4.6.3nRESET Output from PMIC to the Intel® PXA27x Processor

nRESET is an active-low signal from the PMIC to the PXA27x processor that tells the processor to enter the hardware-reset state. The assertion of nRESET cannot be gated and causes the PXA27x processor to enter a complete and unconditional reset state. The nRESET signal contains an internal resistive pull-up that is always active (no pull-up required on the system module or in the PMIC).

nRESET is a hard reset that can cause the system to lose state or data when asserted. It is asserted for a cold start power-on event, or if for any reason the user pushes the system reset button. The power controller must assert nRESET for both events.

nRESET must remain asserted for at least 50 ms when asserted. When not asserted, nRESET is pulled up internally to VCC_REG. VCC_REG is normally powered from VCC_IO, except when in deep-sleep mode, where VCC_REG is powered from VCC_BATT.

All PXA27x processor internal registers and processes are held at their defined reset conditions during hardware reset. While the nRESET signal is asserted, the only activity inside the PXA27x processor is the stabilization of the 13.000 MHz oscillator and phase-locked loops. The remaining internal clocks are stopped and the processor is fully static. Additionally, all signals assume their reset conditions, and the nBATT_FAULT and nVDD_FAULT signals are ignored. The nRESET_OUT signal from the PXA27x processor is asserted when the nRESET input signal is asserted.

4.7Universal Subscriber Identity Module (USIM)

The PXA27x processor provides signals to control an external regulator that powers the USIM card interface used in many digital cell phones. The VCC_USIM regulator output voltage is set to 1.8 V or 3.0 V or disabled (0 V) under software control. The software voltage control is implemented either by using I2C commands or by decoding the PXA27x processor UVS0, nUVS1, and nUVS2 outputs in the PMIC.

The regulator must drive VCC_USIM to ground when UVS0 is driven high. The regulator must drive VCC_USIM to 1.8 V when nUVS1 is driven low. The regulator must drive VCC_USIM to

3.0V when nUVS2 is driven low. The PXA27x processor USIM interface asserts only one of these signals at a time such that they can be used to control the gate of simple FET switches directly.

Note: The regulator that generates VCC_USIM must be disabled using SYS_EN or an I2C command when the PXA27x processor enters deep-sleep mode. During deep sleep, the UVS0, nUVS1, and nUVS2 outputs are not driven and cannot control the VCC_USIM regulator.

4.8Power Manager Capacitor Signals

This section describes connection of external capacitors to PXA27x processor signals. These capacitors do not have a direct design impact on a PMIC but are included here for completeness.

Application Note

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Contents Application Note Intel PXA27x Processor Family Power RequirementsApplication Note Contents Figures Naming Conventions IntroductionIntel PXA27x Processor Power Supply Domains External Power Supply DescriptionsPower Domain Enable1 Units Specified Levels Tolerance Volts Pxtal PLLSram DMAIntel PXA27x Processor Power Supplies Power Domains and System Voltage/Current RequirementsVoltage Description Intel PXA27x Processor Voltage Domains Sheet 1Intel PXA27x Processor Voltage Domains Sheet 2 Power Supply Configuration in a Minimal SystemRegulators Required to Power the Intel PXA27x Processor Modeling Intel PXA27x processor power consumptionIntel PXA27x Processor Vcccore Supply Current Regulator DescriptionSupply Current For Each Power Domain Frequency Dhrystones Power MPEG4 Decode Power StressIntel PXA27x Processor Vcccore Supply Current Intel PXA27x Processor Supply Current For Each Power Domain Default Reset ValuesName Functional Units Current mA @ Power VccbattMain Battery Backup BatteryBatteries Battery Chargers and Main Power Possible Backup Battery ConfigurationsBackup Battery Description Typical Battery and External Regulator Configuration Intel PXA27x Processor Operating Modes Intel PXA27x Processor Low Power Operating ModesPower Controller Interface Signals CPDIS=1CPDIS=0 System Power Enable Sysen / GPIO2 Power Enable PwrenPower Manager I2C Clock Pwrscl / GPIO3 Power Controller Interface SignalsOn, Off, and Reset Power Manager I2C Data Pwrsda / GPIO4User-Initiated Hard Reset Input System-Level Considerations for I2CPower Manager Capacitor Signals NRESET Output from Pmic to the Intel PXA27x ProcessorUniversal Subscriber Identity Module Usim Power Mode Sequencing Power-OnCold-Start Power-On and Hardware Reset Vcccore Vccpll Vccsram Initial Power Up and Deep Sleep Exit SequenceHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Pwrdel SysdelSleep Entry and Exit Sleep and Deep SleepDeep Sleep Entry and Exit Vcccore Regulator and Dynamic Voltage Management Dynamic Voltage Management DVMIntel PXA27x Processor Voltage Manager Power Manager I2C Interface Fault ManagementNVDDFAULT DVM SequencingPower Management Integrated Circuit Requirements NBATTFAULTGeneral Pmic Characteristics Features of a Pmic General Pmic CharacteristicsCharacteristic Description DVM Control Register Programmable Voltage ControlOther Aspects of an Integrated Power Controller SummaryDVM Control and Status Register Intel PXA27x Processor Family Power Requirements
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