Intel PXA27X manual Intel PXA27x Processor Family Power Requirements

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Intel® PXA27x Processor Family Power Requirements

1.The PMIC asserts nRESET.

2.The PXA27x processor asserts the nRESET_OUT1 signal. The time between nRESET assertion and nRESET_OUT assertion depends on whether this event the PXA27x processor was previously running or whether this is an initial power up event.

3.The PMIC de-asserts nRESET after a minimum of 50 ms from nRESET assertion.

4.The internal processor PMU waits for the 13.000 MHz oscillator and internal PLLs to stabilize, if needed.

5.The PXA27x processor de-asserts the nRESET_OUT signal.

The timing for hardware reset is shown in the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification. The PXA27x processor power manager sleep reset state is shown in Figure 4. The timing between nRESET assertion and nRESET_OUT assertion is shown in the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification data sheet.

Application Note

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Contents Application Note Intel PXA27x Processor Family Power RequirementsApplication Note Contents Figures Naming Conventions IntroductionExternal Power Supply Descriptions Intel PXA27x Processor Power Supply DomainsPower Domain Enable1 Units Specified Levels Tolerance Volts Pxtal PLLSram DMAIntel PXA27x Processor Power Supplies Power Domains and System Voltage/Current RequirementsVoltage Description Intel PXA27x Processor Voltage Domains Sheet 1Intel PXA27x Processor Voltage Domains Sheet 2 Power Supply Configuration in a Minimal SystemRegulators Required to Power the Intel PXA27x Processor Modeling Intel PXA27x processor power consumptionIntel PXA27x Processor Vcccore Supply Current Regulator DescriptionFrequency Dhrystones Power MPEG4 Decode Power Stress Supply Current For Each Power DomainIntel PXA27x Processor Vcccore Supply Current Intel PXA27x Processor Supply Current For Each Power Domain Default Reset ValuesName Functional Units Current mA @ Power VccbattBackup Battery Main BatteryBatteries Possible Backup Battery Configurations Battery Chargers and Main PowerBackup Battery Description Typical Battery and External Regulator Configuration Intel PXA27x Processor Operating Modes Intel PXA27x Processor Low Power Operating ModesCPDIS=1 Power Controller Interface SignalsCPDIS=0 System Power Enable Sysen / GPIO2 Power Enable PwrenPower Manager I2C Clock Pwrscl / GPIO3 Power Controller Interface SignalsOn, Off, and Reset Power Manager I2C Data Pwrsda / GPIO4User-Initiated Hard Reset Input System-Level Considerations for I2CNRESET Output from Pmic to the Intel PXA27x Processor Power Manager Capacitor SignalsUniversal Subscriber Identity Module Usim Power-On Power Mode SequencingCold-Start Power-On and Hardware Reset Vcccore Vccpll Vccsram Initial Power Up and Deep Sleep Exit SequenceHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Pwrdel SysdelSleep Entry and Exit Sleep and Deep SleepDeep Sleep Entry and Exit Vcccore Regulator and Dynamic Voltage Management Dynamic Voltage Management DVMIntel PXA27x Processor Voltage Manager Power Manager I2C Interface Fault ManagementNVDDFAULT DVM SequencingNBATTFAULT Power Management Integrated Circuit RequirementsGeneral Pmic Characteristics General Pmic Characteristics Features of a PmicCharacteristic Description DVM Control Register Programmable Voltage ControlSummary Other Aspects of an Integrated Power ControllerDVM Control and Status Register Intel PXA27x Processor Family Power Requirements