Intel PXA27X manual Sleep and Deep Sleep, Sleep Entry and Exit

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Intel® PXA27x Processor Family Power Requirements

5.2Sleep and Deep Sleep

The sleep and deep-sleep modes reduce power consumption by powering down most units in the PXA27x processor. However, the real-time clock, timekeeping oscillator (32.768 kHz), and PMU circuits remain active. The processor oscillator (13.000 MHz), power manager I2C, and JTAG units may also be active. One, two, or four banks of internal SRAM can (optionally) remain powered in sleep mode to retain data, at the expense of approximately 100 ∝W per bank.

In sleep and deep-sleep modes, the PXA27x processor power supplies VCC_CORE, VCC_SRAM, and VCC_PLL can be disabled to achieve greater system power savings. In deep- sleep mode, the system power supplies VCC_IO, VCC_LCD, VCC_USIM, VCC_BB, VCC_USB, and VCC_MEM can also be powered down for additional power savings. The PXA27x processor then uses VCC_BATT to power an internal DC-to-DC converter, optimized for high efficiency at low power, to create the internal supplies.

The penalty for removing power from VCC_CORE and VCC_SRAM is that the processor execution state is lost. Once the processor activity has stopped, recovery from sleep and deep-sleep modes must be through an external wakeup event or a real-time clock timer event that initiates a sleep reset sequence to boot the PXA27x processor again.

Retaining SDRAM contents while in sleep and deep-sleep modes requires an additional, efficient low-current supply powered from either the main or backup battery. Pull down the PXA27x processor SDCKE signal to retain SDRAM contents while in sleep and deep sleep.

Before entering the sleep or deep-sleep modes, software must program the appropriate registers within the PXA27x processor to:

•Set up delay timers

•Shut off internal functional blocks

•Specify the wakeup sources for exiting sleep or deep sleep

Software initiates entry into sleep or deep sleep (for example, the user presses the OFF button and closes the unit cover), or by a hardware event such as assertion of the nVDD_FAULT or nBATT_FAULT signals from the PMIC. See Section 7.0 for fault conditions and interaction between the PXA27x processor and the PMIC during those events.

5.2.1Sleep Entry and Exit

Prior to entering sleep mode, the PXA27x processor prepares the PMIC by specifying which additional system regulators, if any, are to be disabled or shut down when the PMIC is commanded to go into sleep mode. The set of regulators to be turned off can be fixed in PMIC hardware, or it might be programmable. If programmable, a register in the PMIC is loaded via I2C to specify which regulators turn off. For optimal power savings during sleep, enable and disable the VCC_CORE, VCC_PLL, and VCC_SRAM regulators using PWR_EN, but other regulators in the system may or may not require enabling/disabling, depending upon system design. For example, if a memory device or peripheral must retain its contents during sleep under certain conditions, it may require another regulator that is software controllable.

The PXA27x processor places DRAM memory into self-refresh mode. Note that in self-refresh mode, the DRAM must still be powered, but power decreases substantially. Alternatively, if DRAM contents do not need to be preserved, the processor places the DRAMs into deep-power- down mode. Doing so reduces DRAM power to microamps, even though voltage from the PMIC is still maintained on the DRAM power signals.

Application Note

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Contents Application Note Intel PXA27x Processor Family Power RequirementsApplication Note Contents Figures Naming Conventions IntroductionIntel PXA27x Processor Power Supply Domains External Power Supply DescriptionsPower Domain Enable1 Units Specified Levels Tolerance Volts DMA PLLPxtal SramIntel PXA27x Processor Power Supplies Power Domains and System Voltage/Current RequirementsVoltage Description Intel PXA27x Processor Voltage Domains Sheet 1Intel PXA27x Processor Voltage Domains Sheet 2 Power Supply Configuration in a Minimal SystemRegulator Description Modeling Intel PXA27x processor power consumptionRegulators Required to Power the Intel PXA27x Processor Intel PXA27x Processor Vcccore Supply CurrentSupply Current For Each Power Domain Frequency Dhrystones Power MPEG4 Decode Power StressIntel PXA27x Processor Vcccore Supply Current Vccbatt Default Reset ValuesIntel PXA27x Processor Supply Current For Each Power Domain Name Functional Units Current mA @ PowerMain Battery Backup BatteryBatteries Battery Chargers and Main Power Possible Backup Battery ConfigurationsBackup Battery Description Typical Battery and External Regulator Configuration Intel PXA27x Processor Operating Modes Intel PXA27x Processor Low Power Operating ModesPower Controller Interface Signals CPDIS=1CPDIS=0 Power Controller Interface Signals Power Enable PwrenSystem Power Enable Sysen / GPIO2 Power Manager I2C Clock Pwrscl / GPIO3System-Level Considerations for I2C Power Manager I2C Data Pwrsda / GPIO4On, Off, and Reset User-Initiated Hard Reset InputPower Manager Capacitor Signals NRESET Output from Pmic to the Intel PXA27x ProcessorUniversal Subscriber Identity Module Usim Power Mode Sequencing Power-OnCold-Start Power-On and Hardware Reset Vcccore Vccpll Vccsram Initial Power Up and Deep Sleep Exit Sequence Hardware Reset Behavior Intel PXA27x Processor Family Power Requirements Pwrdel SysdelSleep Entry and Exit Sleep and Deep SleepDeep Sleep Entry and Exit Vcccore Regulator and Dynamic Voltage Management Dynamic Voltage Management DVMIntel PXA27x Processor Voltage Manager DVM Sequencing Fault ManagementPower Manager I2C Interface NVDDFAULTPower Management Integrated Circuit Requirements NBATTFAULTGeneral Pmic Characteristics Features of a Pmic General Pmic CharacteristicsCharacteristic Description DVM Control Register Programmable Voltage ControlOther Aspects of an Integrated Power Controller SummaryDVM Control and Status Register Intel PXA27x Processor Family Power Requirements
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