Intel PXA27X manual Fault Management, Power Manager I2C Interface, DVM Sequencing, Nvddfault

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Intel® PXA27x Processor Family Power Requirements

6.3Power Manager I2C Interface

The PXA27x processor communicates with the PMIC using the I2C serial bus. The flexible I2C controller in the processor can pre-load a buffer with a series of commands, or multi-byte commands of any size, up to a total of 32 bytes of command address and data. The I2C controller can be programmed to send a series of commands with programmable intervals between groups of commands to accommodate a variety of different power controllers and regulators.

Refer to the Intel® PXA27x Processor Family EMTS for voltage change timing specifications.

The I2C interface runs in either standard mode at 40 kHz or fast mode at 160 kHz using standard 7- bit addressing. The hardware general call and 10-bit extended addressing are not supported.

6.4DVM Sequencing

The PMIC contains registers that enable, at a minimum, these functions:

•Programming a voltage change from the current voltage to a new voltage

•Programming a ramp rate at which the voltage change occurs

•A GO bit, which once set, triggers the requested voltage change

7.0Fault Management

The PXA27x processor provides two digital status inputs (nBATT_FAULT and nVDD_FAULT) driven by the external PMIC that indicate status of the main battery and the power-supply regulators. These signals permit a combination of hardware and software management of power fault conditions.

Both signals are asserted low to the PXA27x processor inputs. They can be used to place the processor into sleep or deep sleep power-down modes to reduce power quickly and to preserve as much system state or context as possible. Entry into sleep or deep sleep can be initiated directly by the PXA27x processor PMU hardware upon assertion of nBATT_FAULT and nVDD_FAULT, or these events can trigger a software exception handler that saves the system state and issues the command to enter sleep or deep sleep. The PXA27x processor power manager PMCR[BIDAE] and PMCR[VIDAE]1 control bits select between hardware or software handling of these respective fault events.

7.1nVDD_FAULT

nVDD_FAULT signals the PXA27x processor that one or more of its currently enabled supplies are below the minimum regulation limit (supplies that are not enabled do not cause nVDD_FAULT assertion). Functionally, nVDD_FAULT signals the processor when it is safe to exit sleep or when it must enter sleep (using the mechanism selected by the PMCR[VIDAE] setting). nVDD_FAULT is ignored after a wakeup event until the SYS_DEL and PWR_DEL timers expires. The PXA27x processor also has a configuration bit2 that allows nVDD_FAULT to be ignored in sleep mode.

1.See the Intel® PXA27x Processor Family Developer’s Manual

2.The PSLR[IVF] bit; see the Intel® PXA27x Processor Family Developer’s Manual

Application Note

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Contents Application Note Intel PXA27x Processor Family Power RequirementsApplication Note Contents Figures Naming Conventions IntroductionExternal Power Supply Descriptions Intel PXA27x Processor Power Supply DomainsPower Domain Enable1 Units Specified Levels Tolerance Volts DMA PLLPxtal SramIntel PXA27x Processor Power Supplies Power Domains and System Voltage/Current RequirementsVoltage Description Intel PXA27x Processor Voltage Domains Sheet 1Intel PXA27x Processor Voltage Domains Sheet 2 Power Supply Configuration in a Minimal SystemRegulator Description Modeling Intel PXA27x processor power consumptionRegulators Required to Power the Intel PXA27x Processor Intel PXA27x Processor Vcccore Supply CurrentFrequency Dhrystones Power MPEG4 Decode Power Stress Supply Current For Each Power DomainIntel PXA27x Processor Vcccore Supply Current Vccbatt Default Reset ValuesIntel PXA27x Processor Supply Current For Each Power Domain Name Functional Units Current mA @ PowerBackup Battery Main BatteryBatteries Possible Backup Battery Configurations Battery Chargers and Main PowerBackup Battery Description Typical Battery and External Regulator Configuration Intel PXA27x Processor Operating Modes Intel PXA27x Processor Low Power Operating ModesCPDIS=1 Power Controller Interface SignalsCPDIS=0 Power Controller Interface Signals Power Enable PwrenSystem Power Enable Sysen / GPIO2 Power Manager I2C Clock Pwrscl / GPIO3System-Level Considerations for I2C Power Manager I2C Data Pwrsda / GPIO4On, Off, and Reset User-Initiated Hard Reset InputNRESET Output from Pmic to the Intel PXA27x Processor Power Manager Capacitor SignalsUniversal Subscriber Identity Module Usim Power-On Power Mode SequencingCold-Start Power-On and Hardware Reset Vcccore Vccpll Vccsram Initial Power Up and Deep Sleep Exit SequenceHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Pwrdel SysdelSleep Entry and Exit Sleep and Deep SleepDeep Sleep Entry and Exit Vcccore Regulator and Dynamic Voltage Management Dynamic Voltage Management DVMIntel PXA27x Processor Voltage Manager DVM Sequencing Fault ManagementPower Manager I2C Interface NVDDFAULTNBATTFAULT Power Management Integrated Circuit RequirementsGeneral Pmic Characteristics General Pmic Characteristics Features of a PmicCharacteristic Description DVM Control Register Programmable Voltage ControlSummary Other Aspects of an Integrated Power ControllerDVM Control and Status Register Intel PXA27x Processor Family Power Requirements
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