Intel PXA27X manual Power Controller Interface Signals, CPDIS=1, CPDIS=0

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Intel® PXA27x Processor Family Power Requirements

Figure 3. Overview of Power Management Operating Modes

 

any reset

Reset Mode

 

 

 

 

 

 

asserted

 

reset

 

 

 

 

 

 

 

 

de-asserted

 

Idle

 

Normal Mode

Sleep

instruction

 

 

 

 

 

 

instruction

CPDIS=1

 

 

 

 

 

 

 

 

Idle

 

 

 

 

instruction

Standby

Wake-up event

 

Interrupt

CPDIS=0

OR (Fault & xIDAE=1)

instruction

OR (Fault & xIDAE=1)

Wake-up event

 

 

Interrupt

 

OR (Fault & xIDAE=1)

 

 

 

 

 

 

OR (Fault & xIDAE=1)

Wake-up event

 

 

 

 

 

 

 

 

OR (Fault & xIDAE=1)

Deep Idle Mode

Idle Mode

Standby Mode

Sleep Mode

 

 

 

 

Fault & xIDAE=0

Fault & xIDAE=0

 

Fault & xIDAE=0

 

Deep Sleep

 

 

 

Fault & xIDAE=0

 

 

 

instruction OR

 

 

 

(Fault & xIDAE=0)

 

 

 

 

Deep Sleep Mode

4.0Power Controller Interface Signals

The PXA27x processor has an internal power manager unit (PMU) and a set of I/O signals for communicating with an external power management integrated circuit (PMIC). These signals are active for initial power up, certain reset events, device on/off events, and transitions between some operating modes. In addition, two fault signals are required from the PMIC to communicate the onset of power supply problems to the processor. These signals and their function are described fully in Section 7.0.

The PXA27x processor communicates to the power controller using the signals defined in Table 8.

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Application Note

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Contents Intel PXA27x Processor Family Power Requirements Application NoteApplication Note Contents Figures Introduction Naming ConventionsIntel PXA27x Processor Power Supply Domains External Power Supply DescriptionsPower Domain Enable1 Units Specified Levels Tolerance Volts Sram PLLPxtal DMAPower Domains and System Voltage/Current Requirements Intel PXA27x Processor Power SuppliesIntel PXA27x Processor Voltage Domains Sheet 1 Voltage DescriptionPower Supply Configuration in a Minimal System Intel PXA27x Processor Voltage Domains Sheet 2Intel PXA27x Processor Vcccore Supply Current Modeling Intel PXA27x processor power consumptionRegulators Required to Power the Intel PXA27x Processor Regulator DescriptionSupply Current For Each Power Domain Frequency Dhrystones Power MPEG4 Decode Power StressIntel PXA27x Processor Vcccore Supply Current Name Functional Units Current mA @ Power Default Reset ValuesIntel PXA27x Processor Supply Current For Each Power Domain VccbattMain Battery Backup BatteryBatteries Battery Chargers and Main Power Possible Backup Battery ConfigurationsBackup Battery Description Typical Battery and External Regulator Configuration Intel PXA27x Processor Low Power Operating Modes Intel PXA27x Processor Operating ModesPower Controller Interface Signals CPDIS=1CPDIS=0 Power Manager I2C Clock Pwrscl / GPIO3 Power Enable PwrenSystem Power Enable Sysen / GPIO2 Power Controller Interface SignalsUser-Initiated Hard Reset Input Power Manager I2C Data Pwrsda / GPIO4On, Off, and Reset System-Level Considerations for I2CPower Manager Capacitor Signals NRESET Output from Pmic to the Intel PXA27x ProcessorUniversal Subscriber Identity Module Usim Power Mode Sequencing Power-OnCold-Start Power-On and Hardware Reset Initial Power Up and Deep Sleep Exit Sequence Vcccore Vccpll VccsramHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Sysdel PwrdelSleep and Deep Sleep Sleep Entry and ExitDeep Sleep Entry and Exit Dynamic Voltage Management DVM Vcccore Regulator and Dynamic Voltage ManagementIntel PXA27x Processor Voltage Manager NVDDFAULT Fault ManagementPower Manager I2C Interface DVM SequencingPower Management Integrated Circuit Requirements NBATTFAULTGeneral Pmic Characteristics Features of a Pmic General Pmic CharacteristicsCharacteristic Description Programmable Voltage Control DVM Control RegisterOther Aspects of an Integrated Power Controller SummaryDVM Control and Status Register Intel PXA27x Processor Family Power Requirements