Intel PXA27X manual Sysdel, Pwrdel

Page 26

Intel® PXA27x Processor Family Power Requirements

Note: 1) nRESET_OUT assertion is software programmable during processor resets. Refer to the Intel® PXA27x Processor Family Developer’s Manual.

Figure 4. Intel® PXA27x Processor Power Manager Sleep Reset State Diagram

Enable	pll_ok = 1		Normal	Initial
PLL	(Software initiated		Run	Power
			Mode	Up
	deep sleep) OR
				nBATT_FAULT = 0
	nVDD_FAULT = 0

clk_32k_ok = 1

	Deep				nBATT_FAULT = 1		Deep
	Deep				nBATT_FAULT = 0		Deep
	Sleep				nBATT_FAULT = 0		Sleep
					wakeup = 1 &		Batt fault
					wakeup = 1 &
					nBATT_FAULT = 1
		wakeup = 1 &						wakeup = 1 &
		nBATT_FAULT = 1						nBATT_FAULT = 0
					wakeup = 1 &
					wakeup = 1 &
					nBATT_FAULT = 0
	Wakeup						Wakeup
SYS_EN = 1	while				nBATT_FAULT = 1		while
SYS_EN = 1	Batt Fault				nBATT_FAULT = 1		Batt Fault
	de-asserted						asserted

Count		nBATT_FAULT = 0
Down
SYS_DEL

(count_done = 1 & nBATT_FAULT = 1) OR

(all_vcc_hi = 1 & PSSD = 1 & nBATT_FAULT = 1)

PWR_EN

= 1

Assert

nBATT_FAULT = 0

pwr_

All external IO pads use

enable

VCC_IO or corresponding power

supply. Power manager continu

es

to use VCC_BATT

Count		nBATT_FAULT = 0
Down		nBATT_FAULT = 0
PWR_DEL		(nVDD_FAULT = 0) & (count_done = 1)
		(nVDD_FAULT = 0) & (count_done = 1)
(nBATT_FAULT = 1 & nVDD_FAULT = 1) &
(count_done = 1 OR all_vcc_low = 1 & PSSD = 1)			= power manager powered by VCC_CORE
			= power manager powered by VCC_CORE
			= power manager powered by VCC_BATT

26	Application Note

Image 26

Contents Intel PXA27x Processor Family Power Requirements Application NoteApplication Note Contents Figures Introduction Naming ConventionsPower Domain Enable1 Units Specified Levels Tolerance Volts Intel PXA27x Processor Power Supply DomainsExternal Power Supply Descriptions Sram PLLPxtal DMAPower Domains and System Voltage/Current Requirements Intel PXA27x Processor Power SuppliesIntel PXA27x Processor Voltage Domains Sheet 1 Voltage DescriptionPower Supply Configuration in a Minimal System Intel PXA27x Processor Voltage Domains Sheet 2Intel PXA27x Processor Vcccore Supply Current Modeling Intel PXA27x processor power consumptionRegulators Required to Power the Intel PXA27x Processor Regulator DescriptionIntel PXA27x Processor Vcccore Supply Current Supply Current For Each Power DomainFrequency Dhrystones Power MPEG4 Decode Power Stress Name Functional Units Current mA @ Power Default Reset ValuesIntel PXA27x Processor Supply Current For Each Power Domain VccbattBatteries Main BatteryBackup Battery Backup Battery Description Battery Chargers and Main PowerPossible Backup Battery Configurations Typical Battery and External Regulator Configuration Intel PXA27x Processor Low Power Operating Modes Intel PXA27x Processor Operating ModesCPDIS=0 Power Controller Interface SignalsCPDIS=1 Power Manager I2C Clock Pwrscl / GPIO3 Power Enable PwrenSystem Power Enable Sysen / GPIO2 Power Controller Interface SignalsUser-Initiated Hard Reset Input Power Manager I2C Data Pwrsda / GPIO4On, Off, and Reset System-Level Considerations for I2CUniversal Subscriber Identity Module Usim Power Manager Capacitor SignalsNRESET Output from Pmic to the Intel PXA27x Processor Cold-Start Power-On and Hardware Reset Power Mode SequencingPower-On Initial Power Up and Deep Sleep Exit Sequence Vcccore Vccpll VccsramHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Sysdel PwrdelSleep and Deep Sleep Sleep Entry and ExitDeep Sleep Entry and Exit Dynamic Voltage Management DVM Vcccore Regulator and Dynamic Voltage ManagementIntel PXA27x Processor Voltage Manager NVDDFAULT Fault ManagementPower Manager I2C Interface DVM SequencingGeneral Pmic Characteristics Power Management Integrated Circuit RequirementsNBATTFAULT Characteristic Description Features of a PmicGeneral Pmic Characteristics Programmable Voltage Control DVM Control RegisterDVM Control and Status Register Other Aspects of an Integrated Power ControllerSummary Intel PXA27x Processor Family Power Requirements