Intel PXA27X Intel PXA27x Processor Power Supply Domains, External Power Supply Descriptions

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Intel® PXA27x Processor Family Power Requirements

The terms run mode and normal mode are used interchangeably, although normal mode comprises both the run-mode and turbo-mode settings.

2.0Intel® PXA27x Processor Power Supply Domains

Viewed externally, the main or backup battery powers ten power-supply domains. Additional supply domains are present internally, but power for these is derived from the external supply inputs.

All functional units within a power domain connect to the same power supply and are powered up and down together. The PXA27x processor architecture, with its multiple power-supply domains, provides flexibility in system configuration (including selection of I/O voltages for different memory and peripherals) and efficient power management (for instance, flexibility in selecting which peripherals are powered at the same time). Together, these let system designers make power/ complexity trade-offs and optimize a product for intended markets.

Product designers can also choose to strap certain supplies together (to power several domains from a common regulator) to reduce complexity, cost, and the number of regulators in the system. Guidelines showing which supplies can be combined are provided in this document.

A summary of the voltage and tolerance requirements for each external supply input is shown in Table 1. Figure 1 shows the PXA27x processor internal and external power domains and their connections.

Table 1. External Power Supply Descriptions

Power Domain

Enable1

Units

Specified Levels

Tolerance

 

 

 

(Volts)

(%)

VCC_BATT

None

Sleep-control subsystem, oscillators and

3.0

± 25

real-time clock

 

 

 

 

 

 

 

 

 

VCC_IO

SYS_EN

Peripheral input/output

3.0, 3.3

±10 (@ 3.0 V

=10%, -10.3%)

 

 

 

 

 

 

 

 

 

VCC_LCD

SYS_EN

LCD input/output

1.8, 2.5, 3.0, 3.3

+20,-5 (@ 1.8 V)

otherwise ±10

 

 

 

 

 

 

 

 

 

VCC_MEM

SYS_EN

Memory controller input/output

1.8, 2.5, 3.0, 3.3

+20,-5 (@ 1.8 V)

otherwise ±10

 

 

 

 

 

 

 

 

 

VCC_BB

SYS_EN

Baseband interface

1.8, 2.5, 3.0, 3.3

+20,-5 (@ 1.8 V)

otherwise ±10

 

 

 

 

 

 

 

 

 

VCC_USIM

SYS_EN

USIM interface

1.8, 3.0

+20,-5 (@ 1.8 V)

otherwise ±10

 

 

 

 

 

 

 

 

 

VCC_USB

SYS_EN

Differential USB input/output

3.0, 3.3

±10

 

 

 

 

 

VCC_PLL

PWR_EN

Phase-locked loops

1.3

±10

 

 

 

 

 

VCC_SRAM

PWR_EN

Internal SRAM units

1.1

±10

 

 

 

 

 

VCC_CORE

PWR_EN

CPU and other internal units

variable 0.85 – 1.551

-5 +10

NOTE: SYS_EN and PWR_EN are PXA27x processor output control signals.

1.PXA27x processors have different maximum frequencies and VCC_CORE voltages. Refer to both of the Intel® PXA27x Processor Family EMTSs for details.

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Application Note

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Contents Intel PXA27x Processor Family Power Requirements Application NoteApplication Note Contents Figures Introduction Naming ConventionsIntel PXA27x Processor Power Supply Domains External Power Supply DescriptionsPower Domain Enable1 Units Specified Levels Tolerance Volts Sram PLLPxtal DMAPower Domains and System Voltage/Current Requirements Intel PXA27x Processor Power SuppliesIntel PXA27x Processor Voltage Domains Sheet 1 Voltage DescriptionPower Supply Configuration in a Minimal System Intel PXA27x Processor Voltage Domains Sheet 2Intel PXA27x Processor Vcccore Supply Current Modeling Intel PXA27x processor power consumptionRegulators Required to Power the Intel PXA27x Processor Regulator DescriptionSupply Current For Each Power Domain Frequency Dhrystones Power MPEG4 Decode Power StressIntel PXA27x Processor Vcccore Supply Current Name Functional Units Current mA @ Power Default Reset ValuesIntel PXA27x Processor Supply Current For Each Power Domain VccbattMain Battery Backup BatteryBatteries Battery Chargers and Main Power Possible Backup Battery ConfigurationsBackup Battery Description Typical Battery and External Regulator Configuration Intel PXA27x Processor Low Power Operating Modes Intel PXA27x Processor Operating ModesPower Controller Interface Signals CPDIS=1CPDIS=0 Power Manager I2C Clock Pwrscl / GPIO3 Power Enable PwrenSystem Power Enable Sysen / GPIO2 Power Controller Interface SignalsUser-Initiated Hard Reset Input Power Manager I2C Data Pwrsda / GPIO4On, Off, and Reset System-Level Considerations for I2CPower Manager Capacitor Signals NRESET Output from Pmic to the Intel PXA27x ProcessorUniversal Subscriber Identity Module Usim Power Mode Sequencing Power-OnCold-Start Power-On and Hardware Reset Initial Power Up and Deep Sleep Exit Sequence Vcccore Vccpll VccsramHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Sysdel PwrdelSleep and Deep Sleep Sleep Entry and ExitDeep Sleep Entry and Exit Dynamic Voltage Management DVM Vcccore Regulator and Dynamic Voltage ManagementIntel PXA27x Processor Voltage Manager NVDDFAULT Fault ManagementPower Manager I2C Interface DVM SequencingPower Management Integrated Circuit Requirements NBATTFAULTGeneral Pmic Characteristics Features of a Pmic General Pmic CharacteristicsCharacteristic Description Programmable Voltage Control DVM Control RegisterOther Aspects of an Integrated Power Controller SummaryDVM Control and Status Register Intel PXA27x Processor Family Power Requirements