Intel® PXA27x Processor Family Power Requirements
The terms run mode and normal mode are used interchangeably, although normal mode comprises both the
2.0Intel® PXA27x Processor Power Supply Domains
Viewed externally, the main or backup battery powers ten
All functional units within a power domain connect to the same power supply and are powered up and down together. The PXA27x processor architecture, with its multiple
Product designers can also choose to strap certain supplies together (to power several domains from a common regulator) to reduce complexity, cost, and the number of regulators in the system. Guidelines showing which supplies can be combined are provided in this document.
A summary of the voltage and tolerance requirements for each external supply input is shown in Table 1. Figure 1 shows the PXA27x processor internal and external power domains and their connections.
Table 1. External Power Supply Descriptions
Power Domain | Enable1 | Units | Specified Levels | Tolerance | |
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| (Volts) | (%) | |
VCC_BATT | None | 3.0 | ± 25 | ||
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VCC_IO | SYS_EN | Peripheral input/output | 3.0, 3.3 | ±10 (@ 3.0 V | |
=10%, | |||||
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VCC_LCD | SYS_EN | LCD input/output | 1.8, 2.5, 3.0, 3.3 | ||
otherwise ±10 | |||||
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VCC_MEM | SYS_EN | Memory controller input/output | 1.8, 2.5, 3.0, 3.3 | ||
otherwise ±10 | |||||
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VCC_BB | SYS_EN | Baseband interface | 1.8, 2.5, 3.0, 3.3 | ||
otherwise ±10 | |||||
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VCC_USIM | SYS_EN | USIM interface | 1.8, 3.0 | ||
otherwise ±10 | |||||
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VCC_USB | SYS_EN | Differential USB input/output | 3.0, 3.3 | ±10 | |
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VCC_PLL | PWR_EN | 1.3 | ±10 | ||
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VCC_SRAM | PWR_EN | Internal SRAM units | 1.1 | ±10 | |
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VCC_CORE | PWR_EN | CPU and other internal units | variable 0.85 – 1.551 |
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NOTE: SYS_EN and PWR_EN are PXA27x processor output control signals.
1.PXA27x processors have different maximum frequencies and VCC_CORE voltages. Refer to both of the Intel® PXA27x Processor Family EMTSs for details.
6 | Application Note |