Intel PXA27X manual Intel PXA27x Processor Voltage Manager

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Intel® PXA27x Processor Family Power Requirements

•I2C programmable output voltage ramp rate with a default/reset ramp rate of 10mV/∝s. Refer to the Intel® PXA27x Processor Family EMTS for ramp rate specifications

The VCC_CORE regulator must support a minimum set of these six output voltages: 0.85, 0.95, 1.1, 1.2, 1.3, 1.4 and 1.55 V. It is preferable to provide more voltage steps by dividing the range between 0.85 V and 1.55 V using a step size of 10 to 50 mV. The accuracy of each voltage set point must be at least ± 1 voltage step. When using more than the minimum set of five steps it is not necessary to support these five exact step values.

The VCC_CORE regulator must also support programming the voltage ramp rate over a one- decade range of the nominal default value (10mV per ∝s). Ramping is accomplished via a smooth analog ramp driven by an internal ramp generator, or through a series of microsteps of 10-25 mV per microstep, which are performed sequentially after a small delay to make up the requested change in voltage. Faster ramp rates can, in practice, be limited by the capabilities of the regulator and by the amount of bulk capacitance on the VCC_CORE supply.

Controlling the core voltage is accomplished by loading registers in the PMIC via the I2C serial bus. The bus transfers data one byte at a time to the PMIC. Register loads are 8 bits wide, although not all bits need be used by accompanying circuitry. If voltage ramps are comprised of a series of microsteps, the step rate can be programmed as increments of the PMIC internal oscillator used by its voltage converters. Many switching regulators use oscillators in the 500 kHz to 1 MHz range. Section 8.0 contains more information on the recommended PMIC register set and bit fields.

The worst-case load, or maximum di/dt (from the slowest run mode setting to the fastest turbo mode setting) expected is 200 mA per 10 ns.

Note: It may be advantageous to allow scaling of the VCC_CORE domain above 1.55V for debug purposes, which would require the PMIC and associated power circuitry being able to drive VCC_CORE up to 2.0V.

6.2Intel® PXA27x Processor Voltage Manager

The PXA27x processor power manager unit (PMU) includes an internal voltage manager unit with a dedicated I2C interface and a command sequencer. The I2C interface provides the PXA27x processor with dynamic and static voltage control capability, using an I2C module for communicating with the external PMIC. The voltage manager provides these features:

•Static (Halted) or dynamic (operational) voltage change

•Up to 32 I2C commands automatically sent to I2C

•Single and multi-byte I2C command support

•The PXA27x processor I2C commands are user defined to match the format defined by the PMIC.

•Programmable delay between commands

1.A step-down, or voltage dropping converter

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Application Note

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Contents Intel PXA27x Processor Family Power Requirements Application NoteApplication Note Contents Figures Introduction Naming ConventionsIntel PXA27x Processor Power Supply Domains External Power Supply DescriptionsPower Domain Enable1 Units Specified Levels Tolerance Volts Sram PLLPxtal DMAPower Domains and System Voltage/Current Requirements Intel PXA27x Processor Power SuppliesIntel PXA27x Processor Voltage Domains Sheet 1 Voltage DescriptionPower Supply Configuration in a Minimal System Intel PXA27x Processor Voltage Domains Sheet 2Intel PXA27x Processor Vcccore Supply Current Modeling Intel PXA27x processor power consumptionRegulators Required to Power the Intel PXA27x Processor Regulator DescriptionSupply Current For Each Power Domain Frequency Dhrystones Power MPEG4 Decode Power StressIntel PXA27x Processor Vcccore Supply Current Name Functional Units Current mA @ Power Default Reset ValuesIntel PXA27x Processor Supply Current For Each Power Domain VccbattMain Battery Backup BatteryBatteries Battery Chargers and Main Power Possible Backup Battery ConfigurationsBackup Battery Description Typical Battery and External Regulator Configuration Intel PXA27x Processor Low Power Operating Modes Intel PXA27x Processor Operating ModesPower Controller Interface Signals CPDIS=1CPDIS=0 Power Manager I2C Clock Pwrscl / GPIO3 Power Enable PwrenSystem Power Enable Sysen / GPIO2 Power Controller Interface SignalsUser-Initiated Hard Reset Input Power Manager I2C Data Pwrsda / GPIO4On, Off, and Reset System-Level Considerations for I2CPower Manager Capacitor Signals NRESET Output from Pmic to the Intel PXA27x ProcessorUniversal Subscriber Identity Module Usim Power Mode Sequencing Power-OnCold-Start Power-On and Hardware Reset Initial Power Up and Deep Sleep Exit Sequence Vcccore Vccpll VccsramHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Sysdel PwrdelSleep and Deep Sleep Sleep Entry and ExitDeep Sleep Entry and Exit Dynamic Voltage Management DVM Vcccore Regulator and Dynamic Voltage ManagementIntel PXA27x Processor Voltage Manager NVDDFAULT Fault ManagementPower Manager I2C Interface DVM SequencingPower Management Integrated Circuit Requirements NBATTFAULTGeneral Pmic Characteristics Features of a Pmic General Pmic CharacteristicsCharacteristic Description Programmable Voltage Control DVM Control RegisterOther Aspects of an Integrated Power Controller SummaryDVM Control and Status Register Intel PXA27x Processor Family Power Requirements
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