Intel PXA27X manual Programmable Voltage Control, DVM Control Register

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Intel® PXA27x Processor Family Power Requirements

•USB on-the-go charge pump which generates +5.0 V (optional)

The following analog/mixed-signal features are required in many handheld or battery-powered systems, and it is a good idea to provide them in a highly integrated PMIC:

•Power supply for LCD panels or other display types

•USB host VBUS (+5 V) power output

•Power supply for CMOS or CCD image sensor

•Touchscreen controller

•Stereo audio CODEC

•Headset amplifier

•Buzzer/vibration motor driver

•LED drivers

•General purpose input/output (GPIO) signals

•Temperature sensor

8.3Programmable Voltage Control

Maintaining the functionality of the PXA27x processor during any VCC_CORE voltage change (static or dynamic) requires a special external voltage regulator, which must have the features described in Section 6.1. These features are configured through a set of control registers like those described in the following subsections. The PMIC can contain additional registers to control additional system regulators and to provide status bits for system regulators whose voltage is configured by strapping hardware control signals.

8.3.1DVM Control Register 1

This 8-bit register specifies the target voltage for VCC_CORE. The specific bit encoding is left to the PMIC designer. The output of the regulator for VCC_CORE must not go below 0.85 V or above 1.55 V (±10%) regardless of the value set in this register.

Note: This regulator output threshold may be higher depending upon the scope of operation of the PMIC. Refer to Section 6.1 of this document for more information.

8.3.2DVM Control Register 2

This 4-bit to 8-bit register controls the voltage ramp rate. The specific bit encoding is left to the PMIC designer. This register might contain a time delay value that controls the time between output voltage microsteps in implementations that use a discrete voltage ramp rate mechanism. During a voltage change, the regulator output is stepped from the initial voltage to the new set point one microstep at a time to achieve a controlled voltage ramp rate. The input clock is expected to be in the range of 500 kHz to 1 MHz, so it can count out intervals with a minimum of 2 ∝s for each voltage microstep, but the exact delay depends upon the size of the voltage steps used.

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Application Note

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Contents Intel PXA27x Processor Family Power Requirements Application NoteApplication Note Contents Figures Introduction Naming ConventionsExternal Power Supply Descriptions Intel PXA27x Processor Power Supply DomainsPower Domain Enable1 Units Specified Levels Tolerance Volts Sram PLLPxtal DMAPower Domains and System Voltage/Current Requirements Intel PXA27x Processor Power SuppliesIntel PXA27x Processor Voltage Domains Sheet 1 Voltage DescriptionPower Supply Configuration in a Minimal System Intel PXA27x Processor Voltage Domains Sheet 2Intel PXA27x Processor Vcccore Supply Current Modeling Intel PXA27x processor power consumptionRegulators Required to Power the Intel PXA27x Processor Regulator DescriptionFrequency Dhrystones Power MPEG4 Decode Power Stress Supply Current For Each Power DomainIntel PXA27x Processor Vcccore Supply Current Name Functional Units Current mA @ Power Default Reset ValuesIntel PXA27x Processor Supply Current For Each Power Domain VccbattBackup Battery Main BatteryBatteries Possible Backup Battery Configurations Battery Chargers and Main PowerBackup Battery Description Typical Battery and External Regulator Configuration Intel PXA27x Processor Low Power Operating Modes Intel PXA27x Processor Operating ModesCPDIS=1 Power Controller Interface SignalsCPDIS=0 Power Manager I2C Clock Pwrscl / GPIO3 Power Enable PwrenSystem Power Enable Sysen / GPIO2 Power Controller Interface SignalsUser-Initiated Hard Reset Input Power Manager I2C Data Pwrsda / GPIO4On, Off, and Reset System-Level Considerations for I2CNRESET Output from Pmic to the Intel PXA27x Processor Power Manager Capacitor SignalsUniversal Subscriber Identity Module Usim Power-On Power Mode SequencingCold-Start Power-On and Hardware Reset Initial Power Up and Deep Sleep Exit Sequence Vcccore Vccpll VccsramHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Sysdel PwrdelSleep and Deep Sleep Sleep Entry and ExitDeep Sleep Entry and Exit Dynamic Voltage Management DVM Vcccore Regulator and Dynamic Voltage ManagementIntel PXA27x Processor Voltage Manager NVDDFAULT Fault ManagementPower Manager I2C Interface DVM SequencingNBATTFAULT Power Management Integrated Circuit RequirementsGeneral Pmic Characteristics General Pmic Characteristics Features of a PmicCharacteristic Description Programmable Voltage Control DVM Control RegisterSummary Other Aspects of an Integrated Power ControllerDVM Control and Status Register Intel PXA27x Processor Family Power Requirements
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