Intel PXA27X manual Summary, DVM Control and Status Register

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Intel® PXA27x Processor Family Power Requirements

8.3.3DVM Control and Status Register 3

The Control and Status registers contain the GO bit which, once set, activates the voltage change requested by the new voltage in DVM Control register 1, at the ramp rate specified in DVM Control register 2. Additional bits can be added to this register to provide the status for system regulators whose voltage is configured by strapping hardware control signals.

8.3.4Other Aspects of an Integrated Power Controller

If a backup battery or supercap is available in the system, PMIC must be able to switch between the main battery and backup system when the main battery is depleted to ensure VCC_BATT remains powered and the PXA27x processor enters sleep or deep-sleep mode to maximize the life of the backup system.

If the PMIC supports a rechargeable backup battery, the PMIC must be able to charge the backup battery from the main battery until the backup battery reaches a threshold voltage or until the main battery falls below a threshold voltage.

During the initial power-up or during a deep-sleep wakeup sequence when SYS_EN is asserted, ensure that VCC_BATT is driven to the same potential (±200 mV) as VCC_IO. Doing so prevents the PMIC from overdriving the PXA27x processor inputs nVDD_FAULT, nBATT_FAULT, nRESET, GPIO<0>, and GPIO<1> using the VCC_IO supply while the PXA27x processor I/O ring is initially powered from lower VCC_BATT supply. Such an overdriving condition is particularly dangerous because it can result in sourcing current into a non-rechargeable backup battery. Once the wakeup sequence is completed, the PXA27x processor does not draw current or drive I/O from the VCC_BATT input, but this supply must remain available to support sleep and deep-sleep wakeup and reset.

The PMIC must tolerate input voltages of up to 3.75 V on its SYS_EN and PWR_EN input signals to prevent damage when these signals are driven by the PXA27x processor using the maximum backup battery voltage.

9.0Summary

The power management integrated circuit (PMIC) for the PXA27x processor is a highly integrated device with both required and optional features to support the nine power domains on the PXA27x processor, as well as dynamic voltage management features. The PMIC and the PXA27x processor have specific signaling requirements and power-mode sequencing for initial power-on, hardware reset, and sleep and deep sleep entry and exit.

Performance tests and ratings contained within this application note are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, reference www.intel.com/procs/perf/ limits.htm or call (U.S.) 1-800-628-8686 or 1-916-356-3104

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Application Note

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Contents Application Note Intel PXA27x Processor Family Power RequirementsApplication Note Contents Figures Naming Conventions IntroductionPower Domain Enable1 Units Specified Levels Tolerance Volts Intel PXA27x Processor Power Supply DomainsExternal Power Supply Descriptions DMA PLLPxtal SramIntel PXA27x Processor Power Supplies Power Domains and System Voltage/Current RequirementsVoltage Description Intel PXA27x Processor Voltage Domains Sheet 1Intel PXA27x Processor Voltage Domains Sheet 2 Power Supply Configuration in a Minimal SystemRegulator Description Modeling Intel PXA27x processor power consumptionRegulators Required to Power the Intel PXA27x Processor Intel PXA27x Processor Vcccore Supply CurrentIntel PXA27x Processor Vcccore Supply Current Supply Current For Each Power DomainFrequency Dhrystones Power MPEG4 Decode Power Stress Vccbatt Default Reset ValuesIntel PXA27x Processor Supply Current For Each Power Domain Name Functional Units Current mA @ PowerBatteries Main BatteryBackup Battery Backup Battery Description Battery Chargers and Main PowerPossible Backup Battery Configurations Typical Battery and External Regulator Configuration Intel PXA27x Processor Operating Modes Intel PXA27x Processor Low Power Operating ModesCPDIS=0 Power Controller Interface SignalsCPDIS=1 Power Controller Interface Signals Power Enable PwrenSystem Power Enable Sysen / GPIO2 Power Manager I2C Clock Pwrscl / GPIO3System-Level Considerations for I2C Power Manager I2C Data Pwrsda / GPIO4On, Off, and Reset User-Initiated Hard Reset InputUniversal Subscriber Identity Module Usim Power Manager Capacitor SignalsNRESET Output from Pmic to the Intel PXA27x Processor Cold-Start Power-On and Hardware Reset Power Mode SequencingPower-On Vcccore Vccpll Vccsram Initial Power Up and Deep Sleep Exit SequenceHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Pwrdel SysdelSleep Entry and Exit Sleep and Deep SleepDeep Sleep Entry and Exit Vcccore Regulator and Dynamic Voltage Management Dynamic Voltage Management DVMIntel PXA27x Processor Voltage Manager DVM Sequencing Fault ManagementPower Manager I2C Interface NVDDFAULTGeneral Pmic Characteristics Power Management Integrated Circuit RequirementsNBATTFAULT Characteristic Description Features of a PmicGeneral Pmic Characteristics DVM Control Register Programmable Voltage ControlDVM Control and Status Register Other Aspects of an Integrated Power ControllerSummary Intel PXA27x Processor Family Power Requirements
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