Intel PXA27X manual Hardware Reset Behavior

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Intel® PXA27x Processor Family Power Requirements

Note: The nRESET signal must be asserted earlier in the reset sequence for the processor. Refer to the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for power-on reset timing specifications.

The sequence for initial (start-of-life) power-on reset is as follows:

1.VCC_BATT power is applied to the processor and reaches a stable voltage of at least 2.25 V (initiating the power-on reset event) with nRESET asserted from PMIC to the processor.

2.The PMIC must assert nBATT_FAULT because the main battery is not installed.

3.The PMIC de-asserts nRESET after a minimum of 50 ms.

4.The PXA27x processor enables its internal PMU, which waits for the de-assertion of nBATT_FAULT to indicate main battery installation.

5.The fully charged main battery is installed and the PMIC de-asserts nBATT_FAULT.

6.The PXA27x processor asserts SYS_EN to enable the system high-voltage I/O power supplies. The PXA27x processor starts its SYS_DEL countdown timer set to the default 125 ms period.

7.The PMIC enables the regulators driving VCC_IO, and then VCC_LCD, VCC_MEM, VCC_USIM, VCC_BB, and VCC_USB. The latter regulators power on and achieve regulation in any order.

8.After the 125 ms SYS_DEL timer expires, the PXA27x processor asserts PWR_EN to enable the PXA27x processor low-voltage power supplies. Refer to the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for Power-On reset timing specifications. The PXA27x processor starts its PWR_DEL countdown timer set to the default 125 ms period.

9.The PMIC enables the regulators driving VCC_CORE, VCC_PLL, and VCC_SRAM. These regulators power on and achieve regulation in any order.

10.The PMIC de-asserts nVDD_FAULT when all supplies are stable and within regulation specifications.

11.After the 125 ms PWR_DEL timer expires, the PXA27x processor samples the

nVDD_FAULT input. If nVDD_FAULT is asserted, the PXA27x processor returns to sleep or deep-sleep mode; otherwise, the sequence continues.

12.The PXA27x processor continues its power up initialization by enabling the processor (13.000 MHz) oscillator and internal PLLs and switching the I/O supply power for the internal domains from VCC_BATT to VCC_IO.

13.The PXA27x processor de-asserts the nRESET_OUT signal and begins the execution of code from the reset vector.

Refer to the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for power-on reset timing specifications.

5.1.3Hardware Reset Behavior

Hardware reset initiates when the PMIC asserts the nRESET signal low. On assertion of nRESET, the PXA27x processor enters hardware reset state and asserts nRESET_OUT. The PMIC must hold nRESET low long enough to allow internal stabilization and propagation of the reset state, which is a minimum of 50 ms.

The sequence for hardware reset is as follows:

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Application Note

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Contents Intel PXA27x Processor Family Power Requirements Application NoteApplication Note Contents Figures Introduction Naming ConventionsIntel PXA27x Processor Power Supply Domains External Power Supply DescriptionsPower Domain Enable1 Units Specified Levels Tolerance Volts PLL PxtalSram DMAPower Domains and System Voltage/Current Requirements Intel PXA27x Processor Power SuppliesIntel PXA27x Processor Voltage Domains Sheet 1 Voltage DescriptionPower Supply Configuration in a Minimal System Intel PXA27x Processor Voltage Domains Sheet 2Modeling Intel PXA27x processor power consumption Regulators Required to Power the Intel PXA27x ProcessorIntel PXA27x Processor Vcccore Supply Current Regulator DescriptionSupply Current For Each Power Domain Frequency Dhrystones Power MPEG4 Decode Power StressIntel PXA27x Processor Vcccore Supply Current Default Reset Values Intel PXA27x Processor Supply Current For Each Power DomainName Functional Units Current mA @ Power VccbattMain Battery Backup BatteryBatteries Battery Chargers and Main Power Possible Backup Battery ConfigurationsBackup Battery Description Typical Battery and External Regulator Configuration Intel PXA27x Processor Low Power Operating Modes Intel PXA27x Processor Operating ModesPower Controller Interface Signals CPDIS=1CPDIS=0 Power Enable Pwren System Power Enable Sysen / GPIO2Power Manager I2C Clock Pwrscl / GPIO3 Power Controller Interface SignalsPower Manager I2C Data Pwrsda / GPIO4 On, Off, and ResetUser-Initiated Hard Reset Input System-Level Considerations for I2CPower Manager Capacitor Signals NRESET Output from Pmic to the Intel PXA27x ProcessorUniversal Subscriber Identity Module Usim Power Mode Sequencing Power-OnCold-Start Power-On and Hardware Reset Initial Power Up and Deep Sleep Exit Sequence Vcccore Vccpll VccsramHardware Reset Behavior Intel PXA27x Processor Family Power Requirements Sysdel PwrdelSleep and Deep Sleep Sleep Entry and ExitDeep Sleep Entry and Exit Dynamic Voltage Management DVM Vcccore Regulator and Dynamic Voltage ManagementIntel PXA27x Processor Voltage Manager Fault Management Power Manager I2C InterfaceNVDDFAULT DVM SequencingPower Management Integrated Circuit Requirements NBATTFAULTGeneral Pmic Characteristics Features of a Pmic General Pmic CharacteristicsCharacteristic Description Programmable Voltage Control DVM Control RegisterOther Aspects of an Integrated Power Controller SummaryDVM Control and Status Register Intel PXA27x Processor Family Power Requirements
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