Intel 80219 specifications Die Details

Page 12

Intel® 80219 General Purpose PCI Processor

Identification Information

Die Details

Stepping

Part Number

QDF (Q)/

Voltage (V)

Intel® 80219 General

 

Purpose PCI Processor

Notes

Specification Number (SL)

 

 

 

Speed (MHz)

 

 

 

 

 

 

 

 

 

 

 

 

A-0

FW80219M400

Q690

3.3

400

Samples

A-0

FW80219M600

Q691

3.3

600

Samples

A-0

FW80219M400

SL7CL

3.3

400

Production Material

A-0

FW80219M600

SL7CM

3.3

600

Production Material

 

 

 

 

 

 

Device ID Registers

Device and Stepping

Processor Device ID

ATU Device ID

ATU Revision ID

JTAG Device ID

(CP15, Register0 - opcode_2=0)

(ATUDID)

(ATURID)

 

 

 

 

 

 

 

A-0 (400 MHz)

0x69052E20

0x031A

0x00

0x0927E013

A-0 (600 MHz)

0x69052E30

0x031B

0x00

0x0927F013

 

 

 

 

 

12

Specification Update

Image 12
Contents Intel 80219 General Purpose PCI Processor Specification Update Contents This Page Left Intentionally Blank Revision History Preface Affected Documents/Related DocumentsNomenclature Summary Table of Changes Codes Used in Summary TableCore Errata Steppings Status ErrataNon-Core Errata FRAME#Specification Changes Specification ClarificationsDocumentation Changes Identification Information MarkingsDie Details Drain Is Not Flushed Correctly when Stalled in the Pipeline Core ErrataDebug Unit Synchronization with the Txrxctrl Register Extra Circuitry Is Not Jtag Boundary Scan CompliantTrace Buffer Does Not Operate Below 1.3 Data Cache Unit Can Stall for a Single CycleCore Errata Operation may be incorrectly cancelled Disabling the MMU or re-enabling it afterwards Core Errata PBI Issue When Using 16-bit PBI Transactions in PCI Mode Non-Core ErrataContinues running the counter MCU supports a page size of 2 Kbytes for 64-bit mode Vih Minimum Input High Voltage Vih level for the PCI pins Specification Changes Gpio Output Data Register address = Ffff E7CChController Specification Clarifications Application note Hot-Debug for Intel Xscale Core DebugBAR0 Configuration When Using the Messaging Unit MU Reading Unpopulated Sdram Memory BanksWriting to reserved registers can cause unexpected behavior Not completed out of orderDocumentation Changes This Page Left Intentionally Blank