Intel 80219 specifications Vih Minimum Input High Voltage Vih level for the PCI pins

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Intel® 80219 General Purpose PCI Processor

Non-Core Errata

8.Vih Minimum Input High Voltage (Vih) level for the PCI pins

Problem:

The Vih Minimum Input High Voltage (Vih) level for the PCI pins is being tested at 100 mV higher

 

than the minimum Vih level specified in Table 4-3 (DC Specifications for 3.3 V Signaling) of the

 

PCI Local Bus Specification, Revision 2.2. This Vih test limit only applies to cold temperature

 

testing specified to be 0°C.

 

The PCI Local Bus Specification, Revision 2.2 specifies the minimum Vih level to be 0.5 Vcc. The

 

Vcc specification is 3.3 V +/- 10% with the minimum Vcc specification (or minimum power level)

 

being tested at 3.0 V. The minimum Vih level per the PCI Specification should therefore be

 

0.5(3.0 V) or 1.5 V. The 80219 is unable to meet this minimum Vih level at cold temperature

 

testing specified to be 0°C.

Implication:

During cold temperature manufacturing testing, 80219 silicon is subjected to a 0°C environment

 

for an extended period of time. During this time the Vih test is implemented and the junction

 

temperature is at or near the test temperature of 0°C. This junction temperature is considered to be

 

far less than the temperature the 80219 silicon would be subjected to in a customer application

 

under operating conditions.

 

Below is an example calculation showing the expected junction temperature for a customer

 

application operating in an ambient temperature of 0°C:

 

Tj = junctions temperature, Ta = ambient temperature, qja = junction to ambient thermal

 

resistance of the package, P = power at minimum Vcc

 

Tj = Ta + (qja * P) where Ta = 0C, qja = 13.94 C/W assuming 200lfm airflow (see Table 11 of

 

the Intel® 80219 General Purpose PCI Processor Datasheet), P = 3.0 W

 

Tj = 0 + (13.94 C/W * 3.0 C)

 

Tj = 41.82 C

Workaround:

The minimum Vih level for the PCI pins will be tested at the PCI Local Bus Specification,

 

Revision 2.2 specification (0.5 Vcc) plus an additional 100 mV that equates to 1.6 V during cold

 

temperature manufacturing testing.

Status:

NoFix.

Specification Update

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Contents Intel 80219 General Purpose PCI Processor Specification Update Contents This Page Left Intentionally Blank Revision History Nomenclature PrefaceAffected Documents/Related Documents Codes Used in Summary Table Summary Table of ChangesSteppings Status Errata Core ErrataFRAME# Non-Core ErrataDocumentation Changes Specification ChangesSpecification Clarifications Markings Identification InformationDie Details Core Errata Drain Is Not Flushed Correctly when Stalled in the PipelineExtra Circuitry Is Not Jtag Boundary Scan Compliant Debug Unit Synchronization with the Txrxctrl RegisterData Cache Unit Can Stall for a Single Cycle Trace Buffer Does Not Operate Below 1.3Core Errata Operation may be incorrectly cancelled Disabling the MMU or re-enabling it afterwards Core Errata Non-Core Errata PBI Issue When Using 16-bit PBI Transactions in PCI ModeContinues running the counter MCU supports a page size of 2 Kbytes for 64-bit mode Vih Minimum Input High Voltage Vih level for the PCI pins Gpio Output Data Register address = Ffff E7CCh Specification ChangesController Application note Hot-Debug for Intel Xscale Core Debug Specification ClarificationsReading Unpopulated Sdram Memory Banks BAR0 Configuration When Using the Messaging Unit MUNot completed out of order Writing to reserved registers can cause unexpected behaviorDocumentation Changes This Page Left Intentionally Blank