Intel 80219 Trace Buffer Does Not Operate Below 1.3, Data Cache Unit Can Stall for a Single Cycle

Intel® 80219 General Purpose PCI Processor

Core Errata

6.Incorrect Decode of Unindexed Mode, Using Addressing Mode 5, Can Corrupt Protected Registers

Problem:	The instruction decoder incorrectly decodes the valid combination of P=0, U=1 and W=0, when
	using unindexed mode in addressing mode 5 (load and store coprocessor). In this case, the LDC or
	STC should produce consecutive address loads or stores, with no base update until the coprocessor
	signals that it has received enough data. Instead, the instruction gets separated into an LDR/STR
	and a CP access.
	The LDR/STR gets decoded as a post-index address, updating the base register. Due to the
	decoding as post-index, the ‘option’ bits, normally reserved for the coprocessor in unindexed
	mode, become the 8-bit offset value used in the base register update calculation.
	The implication is, that protected registers can be corrupted. This errata can cause the corruption of
	FIQ registers, R13-R14, in user and system modes when the LDC instruction is executed using
	unindexed addressing mode. It can also cause the corruption of FIQ registers, R8-R12, in any mode,
	when the LDC instruction is executed using unindexed addressing. The R13 register in debug mode
	may also be corrupted during an LDC in any mode. In the case of STC, only Rn is corrupted.
	Unexpected memory accesses can also occur. In the case of an LDC, any memory location may be
	accessed, since the FIQ registers may be improperly used as the base register. In the case of an
	STC, the memory word located at Rn+4 is corrupted. This is the memory location immediately
	following the locations which should be modified by STC unindexed.
Workaround:	Do not use unindexed addressing in addressing mode 5 – Load and Store Coprocessor.
Status:	NoFix.

7.Load Immediately Following a DMM Flush Entry is Also Flushed

Problem:	A load that immediately follows a data memory management (DMM) flush entry command, that
	also hits the data TLB, is also flushed. Therefore, the instruction immediately following the flush,
	is also flushed from the data TLB.
Workaround:	All flush entry commands to the data TLB must be followed by two NOPs. The first ensures the
	erratum is not encountered, and the second ensures the speed path is not hit.
Status:	NoFix.

8.Trace Buffer Does Not Operate Below 1.3 V

Problem:	The trace buffer within the debug unit is not guaranteed to operate, due to voltage sensitivity, when
	the core voltage supply is below 1.3 V.
Workaround:	Make sure the voltage is above 1.3 V during debug.
Status:	NoFix.

9.Data Cache Unit Can Stall for a Single Cycle

Problem:	When the data cache unit retries an operation that is in the pending buffer, a single cycle stall
	occurs.
Workaround:	No workaround. This is a performance issue only.
Status:	NoFix.

Specification Update 15