Intel 80219 specifications Summary Table of Changes, Codes Used in Summary Table

Page 7

Intel® 80219 General Purpose PCI Processor

Summary Table of Changes

Summary Table of Changes

The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® 80219 General Purpose PCI Processor product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations:

Codes Used in Summary Table

Stepping

X:

Errata exists in the stepping indicated. Specification Change or

 

Clarification that applies to this stepping.

(No mark)

 

or (Blank box):

This erratum is fixed in listed stepping or specification change does not

 

apply to listed stepping.

Page

(Page):

Page location of item in this document.

Status

Doc:

Document change or update will be implemented.

PlanFix:

This erratum may be fixed in a future stepping of the product.

Fixed:

This erratum has been previously fixed.

NoFix:

There are no plans to fix this erratum.

Row

Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document.

Specification Update

7

Image 7
Contents Intel 80219 General Purpose PCI Processor Specification Update Contents This Page Left Intentionally Blank Revision History Affected Documents/Related Documents PrefaceNomenclature Codes Used in Summary Table Summary Table of ChangesSteppings Status Errata Core ErrataFRAME# Non-Core ErrataSpecification Clarifications Specification ChangesDocumentation Changes Markings Identification InformationDie Details Core Errata Drain Is Not Flushed Correctly when Stalled in the PipelineExtra Circuitry Is Not Jtag Boundary Scan Compliant Debug Unit Synchronization with the Txrxctrl RegisterData Cache Unit Can Stall for a Single Cycle Trace Buffer Does Not Operate Below 1.3Core Errata Operation may be incorrectly cancelled Disabling the MMU or re-enabling it afterwards Core Errata Non-Core Errata PBI Issue When Using 16-bit PBI Transactions in PCI ModeContinues running the counter MCU supports a page size of 2 Kbytes for 64-bit mode Vih Minimum Input High Voltage Vih level for the PCI pins Gpio Output Data Register address = Ffff E7CCh Specification ChangesController Application note Hot-Debug for Intel Xscale Core Debug Specification ClarificationsReading Unpopulated Sdram Memory Banks BAR0 Configuration When Using the Messaging Unit MUNot completed out of order Writing to reserved registers can cause unexpected behaviorDocumentation Changes This Page Left Intentionally Blank