Intel 80219 Non-Core Errata, PBI Issue When Using 16-bit PBI Transactions in PCI Mode

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Intel® 80219 General Purpose PCI Processor

Non-Core Errata

Non-Core Errata

1.The ATU Returns Invalid Data for the DWORD that Target Aborted from the MCU when Using 32-Bit Memory, ECC Enabled and in PCI Mode

The external PCI bus requests a read through the ATU to the MCU, starting at the high DWORD. Remember the MCU is in 32-bit mode. The ATU requests multiple DWORDs since it pre-fetches, but starts at the high DWORD address. The MCU issues two DWORDs. First the high, followed by the low and then a Target Abort, so the DWORD count is two. When the ATU returns the data to the external PCI agent (in PCI Mode ONLY), the logic ONLY disconnects on 64-byte QWORD boundaries. Recall the ATU DWORD count is at two. When the external PCI device returns to get data, the ATU returns the first DWORD and SHOULD disconnect, because it does not have enough data to get to the next QWORD boundary. It does not do this. Instead, it returns invalid data in the high DWORD of the second QWORD (data from a previous fetch) and the transaction is corrupted.

This issue occurs when all of the following conditions exist in the MCU:

1.32-bit memory

2.ECC is enabled

3.The PCI bus is in PCI mode

Workaround: Use 64-bit Memory, PCI-X Mode or ECC disabled.

Status: NoFix.

2.PBI Issue When Using 16-bit PBI Transactions in PCI Mode

Problem:

Under certain conditions, in bound burst and non-burst reads and writes from the PCI bus to the

 

PBI would appear as two writes on the PBI. However, the byte enables are not asserted for the

 

second write.

This happens when:

1.80219 is in PCI mode.

2.Another PCI master is attempting to access the PBI behind the 80219.

3.16-bit mode on PBI.

Workaround: The BE# signals can be used in combination with the PCE#. The BE# prevents the second CE# from being recognized by the Flash. See the Intel® IQ80219 evaluation platform board (IQ80219) schematic for a circuit design to correct this issue.

Status: NoFix.

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Specification Update

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Contents Intel 80219 General Purpose PCI Processor Specification Update Contents This Page Left Intentionally Blank Revision History Nomenclature PrefaceAffected Documents/Related Documents Summary Table of Changes Codes Used in Summary TableCore Errata Steppings Status ErrataNon-Core Errata FRAME#Documentation Changes Specification ChangesSpecification Clarifications Identification Information MarkingsDie Details Drain Is Not Flushed Correctly when Stalled in the Pipeline Core ErrataDebug Unit Synchronization with the Txrxctrl Register Extra Circuitry Is Not Jtag Boundary Scan CompliantTrace Buffer Does Not Operate Below 1.3 Data Cache Unit Can Stall for a Single CycleCore Errata Operation may be incorrectly cancelled Disabling the MMU or re-enabling it afterwards Core Errata PBI Issue When Using 16-bit PBI Transactions in PCI Mode Non-Core ErrataContinues running the counter MCU supports a page size of 2 Kbytes for 64-bit mode Vih Minimum Input High Voltage Vih level for the PCI pins Specification Changes Gpio Output Data Register address = Ffff E7CChController Specification Clarifications Application note Hot-Debug for Intel Xscale Core DebugBAR0 Configuration When Using the Messaging Unit MU Reading Unpopulated Sdram Memory BanksWriting to reserved registers can cause unexpected behavior Not completed out of orderDocumentation Changes This Page Left Intentionally Blank
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