Intel 80219 specifications Preface, Affected Documents/Related Documents, Nomenclature

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Intel® 80219 General Purpose PCI Processor

Preface

Preface

This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents/Related Documents

 

Title

Order

 

 

 

Intel® 80219

General Purpose PCI Processor Developer’s Manual

274017

Intel® 80219

General Purpose PCI Processor Advance Information Datasheet

274018

Intel® 80219

General Purpose PCI Processor Design Guide

274019

Nomenclature

Errata are design defects or errors. These may cause the Intel® 80219 General Purpose PCI Processor1 behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product life cycle, or until a particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.).

1.ARM* architecture compliant.

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Specification Update

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Contents Intel 80219 General Purpose PCI Processor Specification Update Contents This Page Left Intentionally Blank Revision History Preface Affected Documents/Related DocumentsNomenclature Summary Table of Changes Codes Used in Summary TableCore Errata Steppings Status ErrataNon-Core Errata FRAME#Specification Changes Specification ClarificationsDocumentation Changes Identification Information MarkingsDie Details Drain Is Not Flushed Correctly when Stalled in the Pipeline Core ErrataDebug Unit Synchronization with the Txrxctrl Register Extra Circuitry Is Not Jtag Boundary Scan CompliantTrace Buffer Does Not Operate Below 1.3 Data Cache Unit Can Stall for a Single CycleCore Errata Operation may be incorrectly cancelled Disabling the MMU or re-enabling it afterwards Core Errata PBI Issue When Using 16-bit PBI Transactions in PCI Mode Non-Core ErrataContinues running the counter MCU supports a page size of 2 Kbytes for 64-bit mode Vih Minimum Input High Voltage Vih level for the PCI pins Specification Changes Gpio Output Data Register address = Ffff E7CChController Specification Clarifications Application note Hot-Debug for Intel Xscale Core DebugBAR0 Configuration When Using the Messaging Unit MU Reading Unpopulated Sdram Memory BanksWriting to reserved registers can cause unexpected behavior Not completed out of orderDocumentation Changes This Page Left Intentionally Blank