Intel 80219 specifications Core Errata

Intel® 80219 General Purpose PCI Processor

Core Errata

15.Updating the JTAG parallel register requires an extra TCK rising edge

Problem:	IEEE 1149.1 states that the effects of updating all parallel JTAG registers should be seen on the
	falling edge of TCK in the Update-DR state. The Intel Xscale® core parallel JTAG registers
	incorrectly require an extra TCK rising edge to make the update visible. Therefore, operations like
	hold-reset, JTAG break, and vector traps require either an extra TCK cycle by going to
	Run-Test-Idle or by cycling through the state machine again in order to trigger the expected
	hardware behavior.
Workaround:	When the JTAG interface is polled continuously, this erratum has no effect. When not, an extra
	TCK cycle can be caused by going to Run-Test-Idle after writing a parallel JTAG register.
Status:	NoFix.

Specification Update 19