Intel 80219 specifications Writing to reserved registers can cause unexpected behavior

Intel® 80219 General Purpose PCI Processor

Specification Clarifications

6.In-order Delivery not guaranteed for data blocks described by a single DMA descriptor

Issue:	In-order delivery is not guaranteed for data blocks described by a single DMA descriptor that
	crosses a 1 KB boundary. This may result in out of order execution of the DMA transfer. When
	multiple DMA descriptors are used the ordering is maintained with respect to the blocks described
	by each descriptor. When ordering is important, the ordering needs to be maintained by splitting
	the relevant pieces of data into multiple DMA descriptors.
Example	A 100 byte DMA transfer described by a single descriptor with a source address of
	0x3ff8. Since each DMA channel has two 1 KB buffers, the DMA unit breaks this
	transaction at the 1 KB boundary. Therefore, the first buffer might fetch the 8 bytes
	from 0x3ff8-0x3fff and the second buffer might fetch the remaining 92 byes from
	0x4000-0x405C. Both buffers have the ability to access the internal bus, without
	preference (i.e., either buffer may gain access first). Therefore, it is possible the
	92 bytes of data after the 1 KB boundary could be transferred to the destination
	before the first 8 bytes. However, the transaction is completed and all data has been
	copied to the correct address when the descriptor completes (i.e., descriptors are
	not completed out of order).
Status:	When a data delivery sequence is required, descriptors should be used to ensure sequenced arrival
	(e.g., in the example above), break the data into blocks then use multiple descriptors linked in the
	correct order to ensure sequential data delivery.

7.Writing to reserved registers can cause unexpected behavior

Issue:	The Intel® 80219 General Purpose PCI Processor contains several reserved registers. The Intel®
	80219 General Purpose PCI Processor Developer’s Manual (Section 15.5 Table 273) states that
	memory map register locations FFFFE800H - FFFFE8FFH are reserved. Writing to these can cause
	the processor to enter an undesired state.
Status:	NoFix.

28 Specification Update