Intel 80219 specifications Disabling the MMU or re-enabling it afterwards

Intel® 80219 General Purpose PCI Processor

Core Errata

13.Accesses to the CP15 ID register with opcode2 > 0b001 returns unpredictable values

Problem:	The ARM Architecture Reference Manual (ARM DDI 0100E) states the following in chapter B-2,
	section 2.3:
	“If an <opcode2> value corresponding to an unimplemented or reserved ID register is
	encountered, the System Control processor returns the value of the main ID register.
	ID registers other than the main ID register are defined so that when implemented, their value
	cannot be equal to that of the main ID register. Software can therefore determine whether they
	exist by reading both the main ID register and the desired register and comparing their values.
	If the two values are not equal, the desired register exists.”
	The Intel Xscale® core does not implement any CP15 ID code registers other than the Main ID
	register (opcode2 = 0b000) and the Cache Type register (opcode2 = 0b001). When any of the
	unimplemented registers are accessed by software (e.g., mrc p15, 0, r3, c15, c15, 2), the value of
	the Main ID register should be returned. Instead, an unpredictable value is returned.
Workaround:	No workaround.
Status:	NoFix.

14.Disabling and re-enabling the MMU can hang the core or cause it to execute the wrong code

Problem:	When the MMU is disabled, via the CP15 control register (CP15, CR1, opcode_2 = 0, bit 0), after
	being enabled, certain timing cases can cause the processor to hang. In addition to this, re-enabling
	the MMU after disabling it can cause the processor to fetch and execute code from the wrong
	physical address. To avoid these issues, the code sequence below needs to be used whenever
	disabling the MMU or re-enabling it afterwards.
Workaround:	The following code sequence can be used to disable and/or re-enable the MMU safely. The
	alignment of the mcr instruction that disables or re-enables the MMU needs to be controlled
	carefully, so that it resides in the first word of an instruction cache line.
	@ The following code sequence takes r0 as a parameter. The value of r0 is written
	@ to the CP15 control register to either enable or disable the MMU.
	mcr	p15, 0, r0, c10, c4, 1@ unlock I-TLB
	mcr	p15, 0, r0, c8, c5, 0@ invalidate I-TLB
		mrc p15,	0,	r0,	c2,	c0,	0@	CPWAIT
		mov r0, r0
		sub pc, pc, #4
	b	1f				@ branch to aligned code
	.align 5
	1:
	mcr	p15, 0, r0, c1, c0, 0@ enable/disable MMU, caches
		mrc p15,	0,	r0,	c2,	c0,	0@	CPWAIT
		mov r0, r0
		sub pc, pc, #4
Status:	NoFix.

18 Specification Update