Intel 80219 specifications Controller

Page 25

Intel® 80219 General Purpose PCI Processor

Specification Changes

Note: The host BIOS does not require any modifications to accommodate this implementation. All the responsibility for I/O device configuration and resource falls to the 80219 firmware.

Figure 2. Intel® 80219 General Purpose PCI Processor P_BMI Signal Implementation for Intel® 80219 General Purpose PCI Processor B-0/B-1 Stepping

I/O

 

GPOD Register

 

 

Bit 0

 

Controller

 

 

 

 

 

IDSEL

 

Enable P BMI

Intel® 80219

R1

General Purpose

PCI Processor

 

 

(B-0 / B-1 Stepping)

 

P_BMI Signal (AE23)

P_BMI

 

 

 

Control

 

 

 

Logic

 

AD[11+x]

 

GNT#

 

 

PCI-X Bus AD[64:0]

 

 

 

 

 

B2845-01

Specification Update

25

Image 25
Contents Intel 80219 General Purpose PCI Processor Specification Update Contents This Page Left Intentionally Blank Revision History Affected Documents/Related Documents PrefaceNomenclature Codes Used in Summary Table Summary Table of ChangesSteppings Status Errata Core ErrataFRAME# Non-Core ErrataSpecification Clarifications Specification ChangesDocumentation Changes Markings Identification InformationDie Details Core Errata Drain Is Not Flushed Correctly when Stalled in the PipelineExtra Circuitry Is Not Jtag Boundary Scan Compliant Debug Unit Synchronization with the Txrxctrl RegisterData Cache Unit Can Stall for a Single Cycle Trace Buffer Does Not Operate Below 1.3Core Errata Operation may be incorrectly cancelled Disabling the MMU or re-enabling it afterwards Core Errata Non-Core Errata PBI Issue When Using 16-bit PBI Transactions in PCI ModeContinues running the counter MCU supports a page size of 2 Kbytes for 64-bit mode Vih Minimum Input High Voltage Vih level for the PCI pins Gpio Output Data Register address = Ffff E7CCh Specification ChangesController Application note Hot-Debug for Intel Xscale Core Debug Specification ClarificationsReading Unpopulated Sdram Memory Banks BAR0 Configuration When Using the Messaging Unit MUNot completed out of order Writing to reserved registers can cause unexpected behaviorDocumentation Changes This Page Left Intentionally Blank