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Intel® 80219 General Purpose PCI Processor

Documentation Changes

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30	Specification Update

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Contents Intel 80219 General Purpose PCI Processor Specification Update Contents This Page Left Intentionally Blank Revision History Preface Affected Documents/Related DocumentsNomenclature Summary Table of Changes Codes Used in Summary TableCore Errata Steppings Status ErrataNon-Core Errata FRAME#Specification Changes Specification ClarificationsDocumentation Changes Identification Information MarkingsDie Details Drain Is Not Flushed Correctly when Stalled in the Pipeline Core ErrataDebug Unit Synchronization with the Txrxctrl Register Extra Circuitry Is Not Jtag Boundary Scan CompliantTrace Buffer Does Not Operate Below 1.3 Data Cache Unit Can Stall for a Single CycleCore Errata Operation may be incorrectly cancelled Disabling the MMU or re-enabling it afterwards Core Errata PBI Issue When Using 16-bit PBI Transactions in PCI Mode Non-Core ErrataContinues running the counter MCU supports a page size of 2 Kbytes for 64-bit mode Vih Minimum Input High Voltage Vih level for the PCI pins Specification Changes Gpio Output Data Register address = Ffff E7CChController Specification Clarifications Application note Hot-Debug for Intel Xscale Core DebugBAR0 Configuration When Using the Messaging Unit MU Reading Unpopulated Sdram Memory BanksWriting to reserved registers can cause unexpected behavior Not completed out of orderDocumentation Changes This Page Left Intentionally Blank