Intel 80219 specifications Documentation Changes

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Intel® 80219 General Purpose PCI Processor

Documentation Changes

Documentation Changes

None for this revision of this specification update.

Specification Update

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Contents Intel 80219 General Purpose PCI Processor Specification Update Contents This Page Left Intentionally Blank Revision History Nomenclature PrefaceAffected Documents/Related Documents Codes Used in Summary Table Summary Table of ChangesSteppings Status Errata Core ErrataFRAME# Non-Core ErrataDocumentation Changes Specification ChangesSpecification Clarifications Markings Identification InformationDie Details Core Errata Drain Is Not Flushed Correctly when Stalled in the PipelineExtra Circuitry Is Not Jtag Boundary Scan Compliant Debug Unit Synchronization with the Txrxctrl RegisterData Cache Unit Can Stall for a Single Cycle Trace Buffer Does Not Operate Below 1.3Core Errata Operation may be incorrectly cancelled Disabling the MMU or re-enabling it afterwards Core Errata Non-Core Errata PBI Issue When Using 16-bit PBI Transactions in PCI ModeContinues running the counter MCU supports a page size of 2 Kbytes for 64-bit mode Vih Minimum Input High Voltage Vih level for the PCI pins Gpio Output Data Register address = Ffff E7CCh Specification ChangesController Application note Hot-Debug for Intel Xscale Core Debug Specification ClarificationsReading Unpopulated Sdram Memory Banks BAR0 Configuration When Using the Messaging Unit MUNot completed out of order Writing to reserved registers can cause unexpected behaviorDocumentation Changes This Page Left Intentionally Blank