Intel GD82559ER manual Read Align

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Networking Silicon — GD82559ER

1.Minimum transfer of one cache line

2.Active byte enable bits (or BE#[3:0] are all low) during MWI access

3.The 82559ER may cross the cache line boundary only if it intends to transfer the next cache line too.

To ensure the above conditions, the 82559ER may use the MWI command only if the following conditions hold:

1.The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16 Dwords.

2.The accessed address is cache line aligned.

3.The 82559ER has at least 8 or 16 Dwords of data in its receive FIFO.

4.There are at least 8 or 16 Dwords of data space left in the system memory buffer.

5.The MWI Enable bit in the PCI Configuration Command register, bit 4, should is set to 1b.

6.The MWI Enable bit in the 82559ER Configure command should is set to 1b. (Details on the Configure command are described in the Software Developer’s Manual.)

If any one of the above conditions does not hold, the 82559ER will use the MW command. If a MWI cycle has started and one of the conditions is no longer valid (for example, the data space in the memory buffer is now less than CLS), then the 82559ER terminates the MWI cycle at the end of the cache line. The next cycle will be either a MW or MWI cycle depending on the conditions listed above.

If the 82559ER started a MW cycle and reached a cache line boundary, it either continues or terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the 82559ER Configure command (byte 3, bit 3). If this bit is set, the 82559ER terminates the MW cycle and attempts to start a new cycle. The new cycle is a MWI cycle if this bit is set and all of the above listed conditions are met. If the bit is not set, the 82559ER continues the MW cycle across the cache line boundary if required. (Details on the Configure command are described in the Software Developer’s Manual .)

4.2.1.2.2Read Align

The Read Align feature enhances the 82559ER’s performance in cache line oriented systems. In these particular systems, starting a PCI transaction on a non-cache line aligned address may cause low performance.

To resolve this performance anomaly, the 82559ER attempts to terminate transmit DMA cycles on a cache line boundary and start the next transaction on a cache line aligned address. This feature is enabled when the Read Align Enable bit is set in the 82559ER Configure command (byte 3, bit 2). (Details on the Configure command are described in the Software Developer’s Manual .)

If this bit is set, the 82559ER operates as follows:

•When the 82559ER is almost out of resources on the transmit DMA (that is, the transmit FIFO is almost full), it attempts to terminate the read transaction on the nearest cache line boundary when possible.

•When the arbitration counter’s feature is enabled (in other words, the Transmit DMA Maximum Byte Count value is set in the Configure command), the 82559ER switches to other pending DMAs on the cache line boundary only.

Note the following:

Datasheet

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Contents GD82559ER Fast Ethernet PCI Controller Product FeaturesMar First release Revision DescriptionContents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet Introduction GD82559ER OverviewSuggested Reading GD82559ER Networkin g Silicon Datasheet Parallel Subsystem Overview GD82559ER Architectural OverviewGD82559ER Networkin g Silicon Fifo Subsystem Overview10/100 Mbps Physical Layer Unit 10/100 Mbps Serial CSMA/CD Unit OverviewGD82559ER Networkin g Silicon Datasheet Address and Data Signals Signal DescriptionsSignal Type Definitions PCI Bus Interface SignalsInterface Control Signals System and Power Management Signals Local Memory Interface SignalsTestability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet D3 to D0 Software Selective GD82559ER Media Access Control Functional Description82559ER Initialization Initialization Effects on 82559ER Units1.1 82559ER Bus Slave Operation Control/Status Register CSR AccessesPCI Interface 1 82559ER Bus OperationsCSR I/O Read Cycle Flash Buffer Read Cycle Flash Buffer AccessesFlash Buffer Write Cycle Retry Premature Accesses1.2 82559ER Bus Master Operation Error HandlingMemory Read Burst Cycle Memory Write and Invalidate Read Align Power Management Event Signal Clockrun Signal4.3 D2 Power State Power States4.1 D0 Power State 4.2 D1 Power StatePCI CLK 4.4 D3 Power StateUnderstanding Power Requirements Power State Conditions 100 Mbs 10 MbsPower State Link 82559ER Functionality Auxiliary Power SignalAlternate Reset Signal Isolate SignalIsolate Signal Behavior to PCI Power Good Signal PCI Reset SignalInterestin g Packet Events Wake-up EventsParallel Flash Interface Serial Eeprom InterfaceLink Status Change Event Subsystem ID Word IA ByteALL 10/100 Mbps CSMA/CD UnitEeprom Words Field Descriptions Bits Name DescriptionLong Frame Reception Full DuplexFlow Control Address Filtering ModificationsMedia Independent Interface MII Management Interface Test Function Description Asynchronous Test ModeGD82559ER Test Port Functionality IntroductionChain Order TriStateNand Tree Nand Tree ChainsAD9 STOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5FLD6 FLD7GD82559ER Networkin g Silicon Datasheet 2 100BASE-TX Transmit Blocks GD82559ER Physical Layer Functional Description100BASE-TX PHY Unit 1 100BASE-TX Transmit Clock GenerationInvalid 2.2 100BASE-TX Scrambler and MLT-3 EncoderVendor Model/Type 2.3 100BASE-TX Transmit FramingTransmit Driver Magnetics Modules3 100BASE-TX Receive Blocks Auto 10/100 Mbps Speed Selection 5 100BASE-TX Link Integrity and Auto-Negotiation Solution10BASE-T Functionality 4 100BASE-TX Collision Detection2.2 10BASE-T Driver and Filter 2 10BASE-T Transmit Blocks3 10BASE-T Receive Blocks 2.1 10BASE-T Manchester Encoder6 10BASE-T Jabber Control Function Auto-Negotiation Functionality4 10BASE-T Collision Detection 5 10BASE-T Link IntegrityParallel Detect and Auto-Negotiation DescriptionAuto-Negotiation and Parallel Detect LED DescriptionLiled T L E D Two and Three LED Schematic DiagramPCI Configuration Registers LAN Ethernet PCI Configuration SpacePCI Vendor ID and Device ID Registers PCI Command Register PCI Command Register Bits PCI Command RegisterPCI Status Register PCI Status Register Bits PCI Status RegisterPCI Revision ID Register PCI Class Code RegisterPCI Cache Line Size Register PCI Latency Timer PCI Header TypePCI Base Address Registers Expansion ROM Base Address Register CSR Memory Mapped Base Address RegisterCSR I/O Mapped Base Address Register Flash Memory Mapped Base Address RegisterER ID Fields Programming PCI Subsystem Vendor ID and Subsystem ID RegistersCapability Pointer Interrupt Line RegisterMaximum Latency Register Power Management Capabilities RegisterInterrupt Pin Register Minimum Grant RegisterPower Management Control and Status Register Power Management Control/Status Register PmcsrData Register Ethernet Data RegisterData Select Data Scale Data Reported D16 D15 Lower Word Offset Control/Status RegistersLAN Ethernet Control/Status Registers D31System Control Block Status Word Flash Control Register System Control Block Command WordSystem Control Block General Pointer PortEarly Receive Interrupt Receive Direct Memory Access Byte CountPower Management Driver Register Power Management Driver RegisterGeneral Status Register General Control RegisterGeneral Status Register General Control RegisterStatistical Counters ER Statistical CountersCounter Description Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet Register 0 Control Register Bit Definitions Bits Name Description DefaultPHY Unit Registers MDI Registers 0Register 1 Status Register Bit Definitions Value 0154H Bits Name Description Default 150Register 2 PHY Identifier Register Bit Definitions Register 3 PHY Identifier Register Bit Definitions10BASE-T MDI Registers 8MDI Register 16 100BASE-TXRegister 17 PHY Unit Special Control Bit Definitions Register 22 Receive Symbol Error Counter Bit Definitions Register 18 PHY Address RegisterBits Register 27 PHY Unit Special Control Bit Definitions Register 23 100BASE-TX Receive Premature End of Frame ErrorCounter Bit Definitions Register 26 Equalizer Control and Status Bit DefinitionsGD82559ER Networking Silicon Datasheet PCI Interface DC Specifications Electrical and Timing SpecificationsDC Specifications General DC SpecificationsFlash/EEPROM Interface DC Specifications LED Voltage/Current CharacteristicsBASE-TX Voltage/Current Characteristics BASE-T Voltage/Current Characteristics Symbol ParameterVCC/2 AC Specifications for PCI Signaling AC Specifications10.4.1.2 X1 Specifications Timing SpecificationsClocks Specifications PCI Clock SpecificationsSymbol PCI Level Units Timing ParametersMeasurement and Test Conditions PCI Timing Parameters Symbol Parameter Min Max UnitsPCI Timings Flash Interface TimingsFlash Timing Parameters Eeprom Timing Parameters Eeprom Interface TimingsBASE-T NLP Timing Parameters Symbol Parameter Condition Min Typ Max UnitsSymbol Parameter Min Typ Max PHY TimingsTDP/TDN Differential HLS Data 1400 Output Peak Jitter Symbol Parameter Condition Min Typ Max Units T64GD82559ER Networking Silicon Datasheet Package Information Package and Pinout InformationPin Name Pinout Information12.2.1 GD82559ER Pin Assignments GD82559ER Pin AssignmentsFLA0 STOP# INTA# DEVSEL# VCC VSSPERR# GNT# VCC FLA1GD82559ER Ball Grid Array Diagram 12.2.2 GD82559ER Ball Grid Array Diagram

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
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