Intel GD82559ER CSR Memory Mapped Base Address Register, CSR I/O Mapped Base Address Register

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GD82559ER — Networkin g Silicon

31

2 1 0

Base Address

 

0

1

 

 

 

 

Reserved

I/O space indicator

Figure 22. Base Address Register for I/O Mapping

Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory or I/O space. Base registers that map to memory space must return a 0b in bit 0. Base registers that map to I/O space must return 1b in bit 0.

Base registers that map into I/O space are always 32 bits wide with bit 0 hardwired to a 1b, bit 1 is reserved and must return 0b on reads, and the other bits are used to map the device into I/O space.

The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For example, a device that wants a 1 Mbyte memory address space would set the most significant 12 bits of the base address register to be configurable, setting the other bits to 0b.

The 82559ER contains BARs for the Control/Status Register (CSR), Flash, and Expansion ROM.

7.1.9.1CSR Memory Mapped Base Address Register

The 82559ER requires one BAR for memory mapping. Software determines which BAR, memory or I/O, is used to access the 82559ER CSR registers.

The memory space for the 82559ER CSR Memory Mapped BAR is 4 Kbyte. It is marked as prefetchable space and is mapped anywhere in the 32-bit memory address space.

7.1.9.2CSR I/O Mapped Base Address Register

The 82559ER requires one BAR for I/O mapping. Software determines which BAR, memory or I.O, is used to access the 82559ER CSR registers. The I/O space for the 82559ER CSR I/O BAR is 64 bytes.

7.1.9.3Flash Memory Mapped Base Address Register

The Flash Memory BAR is a Dword register. The 82559ER physically supports up to a 128 Kbyte Flash device, and requests a 128Kbyte window. The 82559ER always claims a Flash memory window, regardless of whether or not a Flash device is connected (i.e. Flash Base Address Register cannot be disabled).

7.1.9.4Expansion ROM Base Address Register

The Expansion ROM BAR is a Dword register and supports a 128 Kbyte memory via the 82559ER local bus. The Expansion ROM BAR can be disabled by setting the Boot Disable bit of the EEPROM (word AH, bit 11). The 82559ER requests a 1MB window for expansion ROM. If the Boot Disable bit is set, the 82559ER returns a 0b for all bits in this address register, avoiding request of memory allocation for this space.

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Datasheet

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Contents Product Features GD82559ER Fast Ethernet PCI ControllerRevision Description Mar First releaseContents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet GD82559ER Overview IntroductionSuggested Reading GD82559ER Networkin g Silicon Datasheet GD82559ER Architectural Overview Parallel Subsystem OverviewFifo Subsystem Overview GD82559ER Networkin g Silicon10/100 Mbps Serial CSMA/CD Unit Overview 10/100 Mbps Physical Layer UnitGD82559ER Networkin g Silicon Datasheet PCI Bus Interface Signals Signal DescriptionsSignal Type Definitions Address and Data SignalsInterface Control Signals Local Memory Interface Signals System and Power Management SignalsTestability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet Initialization Effects on 82559ER Units GD82559ER Media Access Control Functional Description82559ER Initialization D3 to D0 Software Selective1 82559ER Bus Operations Control/Status Register CSR AccessesPCI Interface 1.1 82559ER Bus Slave OperationCSR I/O Read Cycle Flash Buffer Accesses Flash Buffer Read CycleRetry Premature Accesses Flash Buffer Write CycleError Handling 1.2 82559ER Bus Master OperationMemory Read Burst Cycle Memory Write and Invalidate Read Align Clockrun Signal Power Management Event Signal4.2 D1 Power State Power States4.1 D0 Power State 4.3 D2 Power StatePower State Conditions 100 Mbs 10 Mbs 4.4 D3 Power StateUnderstanding Power Requirements PCI CLKIsolate Signal Auxiliary Power SignalAlternate Reset Signal Power State Link 82559ER FunctionalityPCI Reset Signal Isolate Signal Behavior to PCI Power Good SignalWake-up Events Interestin g Packet EventsSerial Eeprom Interface Parallel Flash InterfaceLink Status Change Event Word IA Byte Subsystem IDBits Name Description 10/100 Mbps CSMA/CD UnitEeprom Words Field Descriptions ALLAddress Filtering Modifications Full DuplexFlow Control Long Frame ReceptionMedia Independent Interface MII Management Interface Introduction Asynchronous Test ModeGD82559ER Test Port Functionality Test Function DescriptionNand Tree Chains TriStateNand Tree Chain OrderFLD7 STOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5FLD6 AD9GD82559ER Networkin g Silicon Datasheet 1 100BASE-TX Transmit Clock Generation GD82559ER Physical Layer Functional Description100BASE-TX PHY Unit 2 100BASE-TX Transmit Blocks2.2 100BASE-TX Scrambler and MLT-3 Encoder InvalidMagnetics Modules 2.3 100BASE-TX Transmit FramingTransmit Driver Vendor Model/Type3 100BASE-TX Receive Blocks 4 100BASE-TX Collision Detection 5 100BASE-TX Link Integrity and Auto-Negotiation Solution10BASE-T Functionality Auto 10/100 Mbps Speed Selection2.1 10BASE-T Manchester Encoder 2 10BASE-T Transmit Blocks3 10BASE-T Receive Blocks 2.2 10BASE-T Driver and Filter5 10BASE-T Link Integrity Auto-Negotiation Functionality4 10BASE-T Collision Detection 6 10BASE-T Jabber Control FunctionDescription Parallel Detect and Auto-NegotiationLED Description Auto-Negotiation and Parallel DetectTwo and Three LED Schematic Diagram Liled T L E DLAN Ethernet PCI Configuration Space PCI Configuration RegistersPCI Vendor ID and Device ID Registers PCI Command Register PCI Command Register PCI Command Register BitsPCI Status Register PCI Status Register PCI Status Register BitsPCI Class Code Register PCI Revision ID RegisterPCI Cache Line Size Register PCI Header Type PCI Latency TimerPCI Base Address Registers Flash Memory Mapped Base Address Register CSR Memory Mapped Base Address RegisterCSR I/O Mapped Base Address Register Expansion ROM Base Address RegisterInterrupt Line Register PCI Subsystem Vendor ID and Subsystem ID RegistersCapability Pointer ER ID Fields ProgrammingMinimum Grant Register Power Management Capabilities RegisterInterrupt Pin Register Maximum Latency RegisterPower Management Control/Status Register Pmcsr Power Management Control and Status RegisterEthernet Data Register Data RegisterData Select Data Scale Data Reported D31 Control/Status RegistersLAN Ethernet Control/Status Registers D16 D15 Lower Word OffsetSystem Control Block Status Word Port System Control Block Command WordSystem Control Block General Pointer Flash Control RegisterPower Management Driver Register Receive Direct Memory Access Byte CountPower Management Driver Register Early Receive InterruptGeneral Control Register General Control RegisterGeneral Status Register General Status RegisterER Statistical Counters Statistical CountersCounter Description Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet MDI Registers 0 Bits Name Description DefaultPHY Unit Registers Register 0 Control Register Bit DefinitionsRegister 1 Status Register Bit Definitions Register 3 PHY Identifier Register Bit Definitions Bits Name Description Default 150Register 2 PHY Identifier Register Bit Definitions Value 0154H100BASE-TX MDI Registers 8MDI Register 16 10BASE-TRegister 17 PHY Unit Special Control Bit Definitions Register 18 PHY Address Register Register 22 Receive Symbol Error Counter Bit DefinitionsBits Register 26 Equalizer Control and Status Bit Definitions Register 23 100BASE-TX Receive Premature End of Frame ErrorCounter Bit Definitions Register 27 PHY Unit Special Control Bit DefinitionsGD82559ER Networking Silicon Datasheet General DC Specifications Electrical and Timing SpecificationsDC Specifications PCI Interface DC SpecificationsLED Voltage/Current Characteristics Flash/EEPROM Interface DC SpecificationsBASE-TX Voltage/Current Characteristics Symbol Parameter BASE-T Voltage/Current CharacteristicsVCC/2 AC Specifications AC Specifications for PCI SignalingPCI Clock Specifications Timing SpecificationsClocks Specifications 10.4.1.2 X1 SpecificationsTiming Parameters Symbol PCI Level UnitsMeasurement and Test Conditions Flash Interface Timings Symbol Parameter Min Max UnitsPCI Timings PCI Timing ParametersFlash Timing Parameters Eeprom Interface Timings Eeprom Timing ParametersPHY Timings Symbol Parameter Condition Min Typ Max UnitsSymbol Parameter Min Typ Max BASE-T NLP Timing ParametersSymbol Parameter Condition Min Typ Max Units T64 TDP/TDN Differential HLS Data 1400 Output Peak JitterGD82559ER Networking Silicon Datasheet Package and Pinout Information Package InformationGD82559ER Pin Assignments Pinout Information12.2.1 GD82559ER Pin Assignments Pin NameFLA1 STOP# INTA# DEVSEL# VCC VSSPERR# GNT# VCC FLA012.2.2 GD82559ER Ball Grid Array Diagram GD82559ER Ball Grid Array Diagram

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
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