Intel GD82559ER manual Signal Descriptions, Signal Type Definitions, PCI Bus Interface Signals

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Networking Silicon —GD82559ER

3.Signal Descriptions

3.1Signal Type Definitions

Type

Name

Description

 

 

 

 

 

 

IN

Input

The input pin is a standard input only signal.

 

 

 

OUT

Output

The output pin is a Totem Pole Output pin and is a standard

active driver.

 

 

 

 

 

T/S

Tri-State

The tri-state pin is a bidirectional, input/output pin.

 

 

 

 

 

The sustained tri-state pin is an active low tri-state signal owned

 

 

and driven by one agent at a time. The agent asserting the S/T/

S/T/S

Sustained Tri-State

S pin low must drive it high at least one clock cycle before

floating the pin. A new agent can only assert an S/T/S signal low

 

 

 

 

one clock cycle after it has been tri-stated by the previous

 

 

owner.

 

 

 

O/D

Open Drain

The open drain pin allows multiple devices to share this signal

as a wired-OR.

 

 

 

 

 

A/I

Analog Input

The analog input pin is used for analog input signals.

 

 

 

A/O

Analog Output

The analog output pin is used for analog output signals.

 

 

 

B

Bias

The bias pin is an input bias.

 

 

 

3.2PCI Bus Interface Signals

3.2.1Address and Data Signals

Symbol

Type

Name and Function

 

 

 

 

 

 

 

 

Address and Data. The address and data lines are multiplexed on

 

 

the same PCI pins. A bus transaction consists of an address phase

 

 

followed by one or more data phases. During the address phase, the

 

 

address and data lines contain the 32-bit physical address. For I/O,

AD[31:0]

T/S

this is a byte address; for configuration and memory, it is a Dword

 

 

address. The 82559ER uses little-endian byte ordering (in other

 

 

words, AD[31:24] contain the most significant byte and AD[7:0]

 

 

contain the least significant byte). During the data phases, the address

 

 

and data lines contain data.

 

 

 

 

 

Command and Byte Enable. The bus command and byte enable

 

 

signals are multiplexed on the same PCI pins. During the address

C/BE[3:0]#

T/S

phase, the C/BE# lines define the bus command. During the data

phase, the C/BE# lines are used as Byte Enables. The Byte Enables

 

 

 

 

are valid for the entire data phase and determine which byte lanes

 

 

carry meaningful data.

 

 

 

 

 

Parity. Parity is even across AD[31:0] and C/BE[3:0]# lines. It is stable

 

 

and valid one clock after the address phase. For data phases, PAR is

 

 

stable and valid one clock after either IRDY# is asserted on a write

PAR

T/S

transaction or TRDY# is asserted on a read transaction.Once PAR is

 

 

valid, it remains valid until one clock after the completion of the current

 

 

data phase. The master drives PAR for address and write data

 

 

phases; and the target, for read data phases.

 

 

 

Datasheet

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Contents GD82559ER Fast Ethernet PCI Controller Product FeaturesMar First release Revision DescriptionContents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet GD82559ER Overview IntroductionSuggested Reading GD82559ER Networkin g Silicon Datasheet Parallel Subsystem Overview GD82559ER Architectural OverviewGD82559ER Networkin g Silicon Fifo Subsystem Overview10/100 Mbps Physical Layer Unit 10/100 Mbps Serial CSMA/CD Unit OverviewGD82559ER Networkin g Silicon Datasheet Signal Type Definitions Signal DescriptionsPCI Bus Interface Signals Address and Data SignalsInterface Control Signals System and Power Management Signals Local Memory Interface SignalsTestability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet 82559ER Initialization GD82559ER Media Access Control Functional DescriptionInitialization Effects on 82559ER Units D3 to D0 Software SelectivePCI Interface Control/Status Register CSR Accesses1 82559ER Bus Operations 1.1 82559ER Bus Slave OperationCSR I/O Read Cycle Flash Buffer Read Cycle Flash Buffer AccessesFlash Buffer Write Cycle Retry Premature Accesses1.2 82559ER Bus Master Operation Error HandlingMemory Read Burst Cycle Memory Write and Invalidate Read Align Power Management Event Signal Clockrun Signal4.1 D0 Power State Power States4.2 D1 Power State 4.3 D2 Power StateUnderstanding Power Requirements 4.4 D3 Power StatePower State Conditions 100 Mbs 10 Mbs PCI CLKAlternate Reset Signal Auxiliary Power SignalIsolate Signal Power State Link 82559ER FunctionalityIsolate Signal Behavior to PCI Power Good Signal PCI Reset SignalInterestin g Packet Events Wake-up EventsSerial Eeprom Interface Parallel Flash InterfaceLink Status Change Event Subsystem ID Word IA ByteEeprom Words Field Descriptions 10/100 Mbps CSMA/CD UnitBits Name Description ALLFlow Control Full DuplexAddress Filtering Modifications Long Frame ReceptionMedia Independent Interface MII Management Interface GD82559ER Test Port Functionality Asynchronous Test ModeIntroduction Test Function DescriptionNand Tree TriStateNand Tree Chains Chain OrderFLD6 STOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5FLD7 AD9GD82559ER Networkin g Silicon Datasheet 100BASE-TX PHY Unit GD82559ER Physical Layer Functional Description1 100BASE-TX Transmit Clock Generation 2 100BASE-TX Transmit BlocksInvalid 2.2 100BASE-TX Scrambler and MLT-3 EncoderTransmit Driver 2.3 100BASE-TX Transmit FramingMagnetics Modules Vendor Model/Type3 100BASE-TX Receive Blocks 10BASE-T Functionality 5 100BASE-TX Link Integrity and Auto-Negotiation Solution4 100BASE-TX Collision Detection Auto 10/100 Mbps Speed Selection3 10BASE-T Receive Blocks 2 10BASE-T Transmit Blocks2.1 10BASE-T Manchester Encoder 2.2 10BASE-T Driver and Filter4 10BASE-T Collision Detection Auto-Negotiation Functionality5 10BASE-T Link Integrity 6 10BASE-T Jabber Control FunctionParallel Detect and Auto-Negotiation DescriptionAuto-Negotiation and Parallel Detect LED DescriptionLiled T L E D Two and Three LED Schematic DiagramLAN Ethernet PCI Configuration Space PCI Configuration RegistersPCI Vendor ID and Device ID Registers PCI Command Register PCI Command Register Bits PCI Command RegisterPCI Status Register PCI Status Register Bits PCI Status RegisterPCI Class Code Register PCI Revision ID RegisterPCI Cache Line Size Register PCI Header Type PCI Latency TimerPCI Base Address Registers CSR I/O Mapped Base Address Register CSR Memory Mapped Base Address RegisterFlash Memory Mapped Base Address Register Expansion ROM Base Address RegisterCapability Pointer PCI Subsystem Vendor ID and Subsystem ID RegistersInterrupt Line Register ER ID Fields ProgrammingInterrupt Pin Register Power Management Capabilities RegisterMinimum Grant Register Maximum Latency RegisterPower Management Control and Status Register Power Management Control/Status Register PmcsrEthernet Data Register Data RegisterData Select Data Scale Data Reported LAN Ethernet Control/Status Registers Control/Status RegistersD31 D16 D15 Lower Word OffsetSystem Control Block Status Word System Control Block General Pointer System Control Block Command WordPort Flash Control RegisterPower Management Driver Register Receive Direct Memory Access Byte CountPower Management Driver Register Early Receive InterruptGeneral Status Register General Control RegisterGeneral Control Register General Status RegisterER Statistical Counters Statistical CountersCounter Description Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet PHY Unit Registers Bits Name Description DefaultMDI Registers 0 Register 0 Control Register Bit DefinitionsRegister 1 Status Register Bit Definitions Register 2 PHY Identifier Register Bit Definitions Bits Name Description Default 150Register 3 PHY Identifier Register Bit Definitions Value 0154HMDI Register 16 MDI Registers 8100BASE-TX 10BASE-TRegister 17 PHY Unit Special Control Bit Definitions Register 18 PHY Address Register Register 22 Receive Symbol Error Counter Bit DefinitionsBits Counter Bit Definitions Register 23 100BASE-TX Receive Premature End of Frame ErrorRegister 26 Equalizer Control and Status Bit Definitions Register 27 PHY Unit Special Control Bit DefinitionsGD82559ER Networking Silicon Datasheet DC Specifications Electrical and Timing SpecificationsGeneral DC Specifications PCI Interface DC SpecificationsLED Voltage/Current Characteristics Flash/EEPROM Interface DC SpecificationsBASE-TX Voltage/Current Characteristics Symbol Parameter BASE-T Voltage/Current CharacteristicsVCC/2 AC Specifications for PCI Signaling AC SpecificationsClocks Specifications Timing SpecificationsPCI Clock Specifications 10.4.1.2 X1 SpecificationsTiming Parameters Symbol PCI Level UnitsMeasurement and Test Conditions PCI Timings Symbol Parameter Min Max UnitsFlash Interface Timings PCI Timing ParametersFlash Timing Parameters Eeprom Timing Parameters Eeprom Interface TimingsSymbol Parameter Min Typ Max Symbol Parameter Condition Min Typ Max UnitsPHY Timings BASE-T NLP Timing ParametersTDP/TDN Differential HLS Data 1400 Output Peak Jitter Symbol Parameter Condition Min Typ Max Units T64GD82559ER Networking Silicon Datasheet Package Information Package and Pinout Information12.2.1 GD82559ER Pin Assignments Pinout InformationGD82559ER Pin Assignments Pin NamePERR# GNT# VCC STOP# INTA# DEVSEL# VCC VSSFLA1 FLA0GD82559ER Ball Grid Array Diagram 12.2.2 GD82559ER Ball Grid Array Diagram

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
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