Intel GD82559ER manual PCI Latency Timer, PCI Header Type, PCI Base Address Registers

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Networking Silicon — GD82559ER

Note: Bit 3 is set to 1b only if the value 00001000b (8H) is written to this register, and bit 4 is set to 1b only if the value of 00010000b (16H) is written to this register. All other bits are read only and will return a value of 0b on read.

This register is expected to be written by the BIOS and the 82559ER driver should not write to it.

7.1.7PCI Latency Timer

The Latency Timer register is a byte wide register. When the 82559ER is acting as a bus master, this register defines the amount of time, in PCI clock cycles, that it may own the bus.

7.1.8PCI Header Type

The Header Type register is a byte read only register. It is hard-coded to equal to 00h for a single function card.

7.1.9PCI Base Address Registers

One of the most important functions for enabling superior configurability and ease of use is the ability to relocate PCI devices in address spaces. The 82559ER contains three types of Base Address Registers (BARs). Two are used for memory mapped resources, and one is used for I/O mapping. Each register is 32 bits wide. The least significant bit in the BAR determines whether it represents a memory or I/O space. The figures below show the layout of a BAR for both memory and I/O mapping. After determining this information, power-up software can map the memory and I/O controllers into available locations and proceed with system boot. To do this mapping in a device independent manner, the base registers for this mapping are placed in the predefined header portion of configuration space. Device drivers can then access this configuration space to determine the mapping of a particular device.

31

4 3 2 1 0

Base Address

 

 

 

0

 

 

 

 

 

Prefetchable

Set to 0b in 82559ER

Type

00- locate anywhere in 32-bit address space

01- locate below 1 Mbyte

10- locate anywhere in 64-bit address space

11- reserved

Memory space indicator

Figure 21. Base Address Register for Memory Mapping

Datasheet

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Contents GD82559ER Fast Ethernet PCI Controller Product FeaturesMar First release Revision DescriptionContents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet Introduction GD82559ER OverviewSuggested Reading GD82559ER Networkin g Silicon Datasheet Parallel Subsystem Overview GD82559ER Architectural OverviewGD82559ER Networkin g Silicon Fifo Subsystem Overview10/100 Mbps Physical Layer Unit 10/100 Mbps Serial CSMA/CD Unit OverviewGD82559ER Networkin g Silicon Datasheet Signal Type Definitions Signal DescriptionsPCI Bus Interface Signals Address and Data SignalsInterface Control Signals System and Power Management Signals Local Memory Interface SignalsTestability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet 82559ER Initialization GD82559ER Media Access Control Functional DescriptionInitialization Effects on 82559ER Units D3 to D0 Software SelectivePCI Interface Control/Status Register CSR Accesses1 82559ER Bus Operations 1.1 82559ER Bus Slave OperationCSR I/O Read Cycle Flash Buffer Read Cycle Flash Buffer AccessesFlash Buffer Write Cycle Retry Premature Accesses1.2 82559ER Bus Master Operation Error HandlingMemory Read Burst Cycle Memory Write and Invalidate Read Align Power Management Event Signal Clockrun Signal4.1 D0 Power State Power States4.2 D1 Power State 4.3 D2 Power StateUnderstanding Power Requirements 4.4 D3 Power StatePower State Conditions 100 Mbs 10 Mbs PCI CLKAlternate Reset Signal Auxiliary Power SignalIsolate Signal Power State Link 82559ER FunctionalityIsolate Signal Behavior to PCI Power Good Signal PCI Reset SignalInterestin g Packet Events Wake-up EventsParallel Flash Interface Serial Eeprom InterfaceLink Status Change Event Subsystem ID Word IA ByteEeprom Words Field Descriptions 10/100 Mbps CSMA/CD UnitBits Name Description ALLFlow Control Full DuplexAddress Filtering Modifications Long Frame ReceptionMedia Independent Interface MII Management Interface GD82559ER Test Port Functionality Asynchronous Test ModeIntroduction Test Function DescriptionNand Tree TriStateNand Tree Chains Chain OrderFLD6 STOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5FLD7 AD9GD82559ER Networkin g Silicon Datasheet 100BASE-TX PHY Unit GD82559ER Physical Layer Functional Description1 100BASE-TX Transmit Clock Generation 2 100BASE-TX Transmit BlocksInvalid 2.2 100BASE-TX Scrambler and MLT-3 EncoderTransmit Driver 2.3 100BASE-TX Transmit FramingMagnetics Modules Vendor Model/Type3 100BASE-TX Receive Blocks 10BASE-T Functionality 5 100BASE-TX Link Integrity and Auto-Negotiation Solution4 100BASE-TX Collision Detection Auto 10/100 Mbps Speed Selection3 10BASE-T Receive Blocks 2 10BASE-T Transmit Blocks2.1 10BASE-T Manchester Encoder 2.2 10BASE-T Driver and Filter4 10BASE-T Collision Detection Auto-Negotiation Functionality5 10BASE-T Link Integrity 6 10BASE-T Jabber Control FunctionParallel Detect and Auto-Negotiation DescriptionAuto-Negotiation and Parallel Detect LED DescriptionLiled T L E D Two and Three LED Schematic DiagramPCI Configuration Registers LAN Ethernet PCI Configuration SpacePCI Vendor ID and Device ID Registers PCI Command Register PCI Command Register Bits PCI Command RegisterPCI Status Register PCI Status Register Bits PCI Status RegisterPCI Revision ID Register PCI Class Code RegisterPCI Cache Line Size Register PCI Latency Timer PCI Header TypePCI Base Address Registers CSR I/O Mapped Base Address Register CSR Memory Mapped Base Address RegisterFlash Memory Mapped Base Address Register Expansion ROM Base Address RegisterCapability Pointer PCI Subsystem Vendor ID and Subsystem ID RegistersInterrupt Line Register ER ID Fields ProgrammingInterrupt Pin Register Power Management Capabilities RegisterMinimum Grant Register Maximum Latency RegisterPower Management Control and Status Register Power Management Control/Status Register PmcsrData Register Ethernet Data RegisterData Select Data Scale Data Reported LAN Ethernet Control/Status Registers Control/Status RegistersD31 D16 D15 Lower Word OffsetSystem Control Block Status Word System Control Block General Pointer System Control Block Command WordPort Flash Control RegisterPower Management Driver Register Receive Direct Memory Access Byte CountPower Management Driver Register Early Receive InterruptGeneral Status Register General Control RegisterGeneral Control Register General Status RegisterStatistical Counters ER Statistical CountersCounter Description Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet PHY Unit Registers Bits Name Description DefaultMDI Registers 0 Register 0 Control Register Bit DefinitionsRegister 1 Status Register Bit Definitions Register 2 PHY Identifier Register Bit Definitions Bits Name Description Default 150Register 3 PHY Identifier Register Bit Definitions Value 0154HMDI Register 16 MDI Registers 8100BASE-TX 10BASE-TRegister 17 PHY Unit Special Control Bit Definitions Register 22 Receive Symbol Error Counter Bit Definitions Register 18 PHY Address RegisterBits Counter Bit Definitions Register 23 100BASE-TX Receive Premature End of Frame ErrorRegister 26 Equalizer Control and Status Bit Definitions Register 27 PHY Unit Special Control Bit DefinitionsGD82559ER Networking Silicon Datasheet DC Specifications Electrical and Timing SpecificationsGeneral DC Specifications PCI Interface DC SpecificationsFlash/EEPROM Interface DC Specifications LED Voltage/Current CharacteristicsBASE-TX Voltage/Current Characteristics BASE-T Voltage/Current Characteristics Symbol ParameterVCC/2 AC Specifications for PCI Signaling AC SpecificationsClocks Specifications Timing SpecificationsPCI Clock Specifications 10.4.1.2 X1 SpecificationsSymbol PCI Level Units Timing ParametersMeasurement and Test Conditions PCI Timings Symbol Parameter Min Max UnitsFlash Interface Timings PCI Timing ParametersFlash Timing Parameters Eeprom Timing Parameters Eeprom Interface TimingsSymbol Parameter Min Typ Max Symbol Parameter Condition Min Typ Max UnitsPHY Timings BASE-T NLP Timing ParametersTDP/TDN Differential HLS Data 1400 Output Peak Jitter Symbol Parameter Condition Min Typ Max Units T64GD82559ER Networking Silicon Datasheet Package Information Package and Pinout Information12.2.1 GD82559ER Pin Assignments Pinout InformationGD82559ER Pin Assignments Pin NamePERR# GNT# VCC STOP# INTA# DEVSEL# VCC VSSFLA1 FLA0GD82559ER Ball Grid Array Diagram 12.2.2 GD82559ER Ball Grid Array Diagram

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
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