Intel GD82559ER manual Testability Port Signals

Page 16

GD82559ER — Networkin g Silicon

Symbol

Type

 

Name and Function

 

 

 

 

 

 

 

 

Flash Address[13]/EEPROM Data Input. During Flash accesses,

FLA[13]/

OUT

this multiplexed pin acts as the Flash Address [13] output signal.

EEDI

During EEPROM accesses, it acts as serial output data to the

 

 

 

EEPROM Data Input signal.

 

 

 

FLA[12:8]

OUT

Flash Address[12:8]. These pins are used as Flash address outputs

to support 128 Kbyte Flash addressing.

 

 

 

 

 

 

 

Flash Address[7]/Clock Enable. This is a multiplexed pin and acts

 

 

as the Flash Address[7] output signal during nominal operation. When

FLA[7]/

T/S

the PCI RST# signal is active, this pin acts as input control over the

CLKENB

FLA[16]/CLK25 output signal. If the FLA[7]/CLKEN pin is connected to

 

 

 

a pull-up resistor (3.3 KΩ), a 25 MHz clock signal is provided on the

 

 

FLA[16]/CLK25 output; otherwise, it is used as FLA[16] output.

 

 

 

FLA[6:2]

OUT

Flash Address[6:2]. These pins are used as Flash address outputs

to support 128

Kbyte Flash addressing.

 

 

 

 

 

 

 

Flash Address[1]/Auxiliary Power. This multiplexed pin acts as the

 

 

Flash Address[1] output signal during nominal operation. When RST is

FLA[1]/

T/S

active (low), it acts as the power supply indicator. If the 82559ER is fed

AUXPWR

PCI power, this pin should be connected to a pull-down resistor; if the

 

 

 

82559ER is fed by auxiliary power, this pin should be connected to a

 

 

pull-up resistor.

 

 

 

FLA[0]

T/S

Flash Address [0]. This pin acts as the Flash Address[0] output

signal during nominal operation.

 

 

 

 

 

EECS

OUT

EEPROM Chip Select. The EEPROM Chip Select signal is used to

assert chip select to the serial EEPROM.

 

 

 

 

 

FLCS#

OUT

Flash Chip Select. The Flash Chip Select signal is active during

Flash.

 

 

 

 

 

 

 

FLOE#

OUT

Flash Output Enable. This pin provides an active low output enable

control (read) to the Flash memory.

 

 

 

 

 

FLWE#

OUT

Flash Write Enable. This pin provides an active low write enable

control to the Flash memory.

 

 

 

 

 

 

3.4Testability Port Signals

Symbol

Type

Name and Function

 

 

 

 

 

 

TEST

IN

Test. If this input pin is high, the 82559ER will enable the test port.

During nominal operation this pin should be connected to a pull-down

 

 

resistor.

 

 

 

TCK

IN

Testability Port Clock. This pin is used for the Testability Port Clock

signal.

 

 

 

 

 

TI

IN

Testability Port Data Input. This pin is used for the Testability Port

Data Input signal.

 

 

 

 

 

TEXEC

IN

Testability Port Execute Enable. This pin is used for the Testability

Port Execute Enable signal.

 

 

 

 

 

TO

OUT

Testability Port Data Output. This pin is used for the Testability Port

Data Output signal.

 

 

 

 

 

10

Datasheet

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Contents Product Features GD82559ER Fast Ethernet PCI ControllerRevision Description Mar First releaseContents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet GD82559ER Overview IntroductionSuggested Reading GD82559ER Networkin g Silicon Datasheet GD82559ER Architectural Overview Parallel Subsystem OverviewFifo Subsystem Overview GD82559ER Networkin g Silicon10/100 Mbps Serial CSMA/CD Unit Overview 10/100 Mbps Physical Layer UnitGD82559ER Networkin g Silicon Datasheet Signal Descriptions Signal Type DefinitionsPCI Bus Interface Signals Address and Data SignalsInterface Control Signals Local Memory Interface Signals System and Power Management SignalsTestability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet GD82559ER Media Access Control Functional Description 82559ER InitializationInitialization Effects on 82559ER Units D3 to D0 Software SelectiveControl/Status Register CSR Accesses PCI Interface1 82559ER Bus Operations 1.1 82559ER Bus Slave OperationCSR I/O Read Cycle Flash Buffer Accesses Flash Buffer Read CycleRetry Premature Accesses Flash Buffer Write CycleError Handling 1.2 82559ER Bus Master OperationMemory Read Burst Cycle Memory Write and Invalidate Read Align Clockrun Signal Power Management Event SignalPower States 4.1 D0 Power State4.2 D1 Power State 4.3 D2 Power State4.4 D3 Power State Understanding Power RequirementsPower State Conditions 100 Mbs 10 Mbs PCI CLKAuxiliary Power Signal Alternate Reset SignalIsolate Signal Power State Link 82559ER FunctionalityPCI Reset Signal Isolate Signal Behavior to PCI Power Good SignalWake-up Events Interestin g Packet EventsSerial Eeprom Interface Parallel Flash InterfaceLink Status Change Event Word IA Byte Subsystem ID10/100 Mbps CSMA/CD Unit Eeprom Words Field DescriptionsBits Name Description ALLFull Duplex Flow ControlAddress Filtering Modifications Long Frame ReceptionMedia Independent Interface MII Management Interface Asynchronous Test Mode GD82559ER Test Port FunctionalityIntroduction Test Function DescriptionTriState Nand TreeNand Tree Chains Chain OrderSTOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5 FLD6FLD7 AD9GD82559ER Networkin g Silicon Datasheet GD82559ER Physical Layer Functional Description 100BASE-TX PHY Unit1 100BASE-TX Transmit Clock Generation 2 100BASE-TX Transmit Blocks2.2 100BASE-TX Scrambler and MLT-3 Encoder Invalid2.3 100BASE-TX Transmit Framing Transmit DriverMagnetics Modules Vendor Model/Type3 100BASE-TX Receive Blocks 5 100BASE-TX Link Integrity and Auto-Negotiation Solution 10BASE-T Functionality4 100BASE-TX Collision Detection Auto 10/100 Mbps Speed Selection2 10BASE-T Transmit Blocks 3 10BASE-T Receive Blocks2.1 10BASE-T Manchester Encoder 2.2 10BASE-T Driver and FilterAuto-Negotiation Functionality 4 10BASE-T Collision Detection5 10BASE-T Link Integrity 6 10BASE-T Jabber Control FunctionDescription Parallel Detect and Auto-NegotiationLED Description Auto-Negotiation and Parallel DetectTwo and Three LED Schematic Diagram Liled T L E DLAN Ethernet PCI Configuration Space PCI Configuration RegistersPCI Vendor ID and Device ID Registers PCI Command Register PCI Command Register PCI Command Register BitsPCI Status Register PCI Status Register PCI Status Register BitsPCI Class Code Register PCI Revision ID RegisterPCI Cache Line Size Register PCI Header Type PCI Latency TimerPCI Base Address Registers CSR Memory Mapped Base Address Register CSR I/O Mapped Base Address RegisterFlash Memory Mapped Base Address Register Expansion ROM Base Address RegisterPCI Subsystem Vendor ID and Subsystem ID Registers Capability PointerInterrupt Line Register ER ID Fields ProgrammingPower Management Capabilities Register Interrupt Pin RegisterMinimum Grant Register Maximum Latency RegisterPower Management Control/Status Register Pmcsr Power Management Control and Status RegisterEthernet Data Register Data RegisterData Select Data Scale Data Reported Control/Status Registers LAN Ethernet Control/Status RegistersD31 D16 D15 Lower Word OffsetSystem Control Block Status Word System Control Block Command Word System Control Block General PointerPort Flash Control RegisterReceive Direct Memory Access Byte Count Power Management Driver RegisterPower Management Driver Register Early Receive InterruptGeneral Control Register General Status RegisterGeneral Control Register General Status RegisterER Statistical Counters Statistical CountersCounter Description Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet Bits Name Description Default PHY Unit RegistersMDI Registers 0 Register 0 Control Register Bit DefinitionsRegister 1 Status Register Bit Definitions Bits Name Description Default 150 Register 2 PHY Identifier Register Bit DefinitionsRegister 3 PHY Identifier Register Bit Definitions Value 0154HMDI Registers 8 MDI Register 16100BASE-TX 10BASE-TRegister 17 PHY Unit Special Control Bit Definitions Register 18 PHY Address Register Register 22 Receive Symbol Error Counter Bit DefinitionsBits Register 23 100BASE-TX Receive Premature End of Frame Error Counter Bit DefinitionsRegister 26 Equalizer Control and Status Bit Definitions Register 27 PHY Unit Special Control Bit DefinitionsGD82559ER Networking Silicon Datasheet Electrical and Timing Specifications DC SpecificationsGeneral DC Specifications PCI Interface DC SpecificationsLED Voltage/Current Characteristics Flash/EEPROM Interface DC SpecificationsBASE-TX Voltage/Current Characteristics Symbol Parameter BASE-T Voltage/Current CharacteristicsVCC/2 AC Specifications AC Specifications for PCI SignalingTiming Specifications Clocks SpecificationsPCI Clock Specifications 10.4.1.2 X1 SpecificationsTiming Parameters Symbol PCI Level UnitsMeasurement and Test Conditions Symbol Parameter Min Max Units PCI TimingsFlash Interface Timings PCI Timing ParametersFlash Timing Parameters Eeprom Interface Timings Eeprom Timing ParametersSymbol Parameter Condition Min Typ Max Units Symbol Parameter Min Typ MaxPHY Timings BASE-T NLP Timing ParametersSymbol Parameter Condition Min Typ Max Units T64 TDP/TDN Differential HLS Data 1400 Output Peak JitterGD82559ER Networking Silicon Datasheet Package and Pinout Information Package InformationPinout Information 12.2.1 GD82559ER Pin AssignmentsGD82559ER Pin Assignments Pin NameSTOP# INTA# DEVSEL# VCC VSS PERR# GNT# VCCFLA1 FLA012.2.2 GD82559ER Ball Grid Array Diagram GD82559ER Ball Grid Array Diagram

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
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