Intel GD82559ER manual ER Statistical Counters, Counter Description

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GD82559ER — Networking Silicon

8.2Statistical Counters

The 82559ER provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the 82559ER when it completes the processing of a frame (that is, when it has completed transmitting a frame on the link or when it has completed receiving a frame). The Statistical Counters are reported to the software on demand by issuing the Dump Statistical Counters command or Dump and Reset Statistical Counters command in the SCB Command Unit Command (CUC) field.

 

Table 14. 82559ER Statistical Counters

 

 

 

ID

Counter

Description

 

 

 

 

 

 

0

Transmit Good Frames

This counter contains the number of frames that were

 

 

transmitted properly on the link. It is updated only after the

 

 

actual transmission on the link is completed, not when the

 

 

frame was read from memory as is done for the Transmit

 

 

Command Block status.

 

 

 

4

Transmit Maximum Collisions

This counter contains the number of frames that were not

 

(MAXCOL) Errors

transmitted because they encountered the configured

 

 

maximum number of collisions.

 

 

 

8

Transmit Late Collisions (LATECOL)

This counter contains the number of frames that were not

 

Errors

transmitted since they encountered a collision later than the

 

 

configured slot time.

 

 

 

12

Transmit Underrun Errors

A transmit underrun occurs because the system bus cannot

 

 

keep up with the transmission. This counter contains the

 

 

number of frames that were either not transmitted or

 

 

retransmitted due to a transmit DMA underrun. If the 82559ER

 

 

is configured to retransmit on underrun, this counter may be

 

 

updated multiple times for a single frame.

 

 

 

16

Transmit Lost Carrier Sense (CRS)

This counter contains the number of frames that were

 

 

transmitted by the 82559ER despite the fact that it detected

 

 

the de-assertion of CRS during the transmission.

 

 

 

20

Transmit Deferred

This counter contains the number of frames that were deferred

 

 

before transmission due to activity on the link.

 

 

 

24

Transmit Single Collisions

This counter contains the number of transmitted frames that

 

 

encountered one collision.

 

 

 

28

Transmit Multiple Collisions

This counter contains the number of transmitted frames that

 

 

encountered more than one collision.

 

 

 

32

Transmit Total Collisions

This counter contains the total number of collisions that were

 

 

encountered while attempting to transmit. This count includes

 

 

late collisions and frames that encountered MAXCOL.

 

 

 

36

Receive Good Frames

This counter contains the number of frames that were

 

 

received properly from the link. It is updated only after the

 

 

actual reception from the link is completed and all the data

 

 

bytes are stored in memory.

 

 

 

40

Receive CRC Errors

This counter contains the number of aligned frames discarded

 

 

because of a CRC error. This counter is updated, if needed,

 

 

regardless of the Receive Unit state. The Receive CRC Errors

 

 

counter is mutually exclusive of the Receive Alignment Errors

 

 

and Receive Short Frame Errors counters.

 

 

 

44

Receive Alignment Errors

This counter contains the number of frames that are both

 

 

misaligned (for example, CRS de-asserts on a non-octal

 

 

boundary) and contain a CRC error. The counter is updated, if

 

 

needed, regardless of the Receive Unit state. The Receive

 

 

Alignment Errors counter is mutually exclusive of the Receive

 

 

CRC Errors and Receive Short Frame Errors counters.

 

 

 

62

Datasheet

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Contents Product Features GD82559ER Fast Ethernet PCI ControllerRevision Description Mar First releaseContents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet Suggested Reading IntroductionGD82559ER Overview GD82559ER Networkin g Silicon Datasheet GD82559ER Architectural Overview Parallel Subsystem OverviewFifo Subsystem Overview GD82559ER Networkin g Silicon10/100 Mbps Serial CSMA/CD Unit Overview 10/100 Mbps Physical Layer UnitGD82559ER Networkin g Silicon Datasheet Signal Descriptions Signal Type DefinitionsPCI Bus Interface Signals Address and Data SignalsInterface Control Signals Local Memory Interface Signals System and Power Management SignalsTestability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet GD82559ER Media Access Control Functional Description 82559ER InitializationInitialization Effects on 82559ER Units D3 to D0 Software SelectiveControl/Status Register CSR Accesses PCI Interface1 82559ER Bus Operations 1.1 82559ER Bus Slave OperationCSR I/O Read Cycle Flash Buffer Accesses Flash Buffer Read CycleRetry Premature Accesses Flash Buffer Write CycleError Handling 1.2 82559ER Bus Master OperationMemory Read Burst Cycle Memory Write and Invalidate Read Align Clockrun Signal Power Management Event SignalPower States 4.1 D0 Power State4.2 D1 Power State 4.3 D2 Power State4.4 D3 Power State Understanding Power RequirementsPower State Conditions 100 Mbs 10 Mbs PCI CLKAuxiliary Power Signal Alternate Reset SignalIsolate Signal Power State Link 82559ER FunctionalityPCI Reset Signal Isolate Signal Behavior to PCI Power Good SignalWake-up Events Interestin g Packet EventsLink Status Change Event Parallel Flash InterfaceSerial Eeprom Interface Word IA Byte Subsystem ID10/100 Mbps CSMA/CD Unit Eeprom Words Field DescriptionsBits Name Description ALLFull Duplex Flow ControlAddress Filtering Modifications Long Frame ReceptionMedia Independent Interface MII Management Interface Asynchronous Test Mode GD82559ER Test Port FunctionalityIntroduction Test Function DescriptionTriState Nand TreeNand Tree Chains Chain OrderSTOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5 FLD6FLD7 AD9GD82559ER Networkin g Silicon Datasheet GD82559ER Physical Layer Functional Description 100BASE-TX PHY Unit1 100BASE-TX Transmit Clock Generation 2 100BASE-TX Transmit Blocks2.2 100BASE-TX Scrambler and MLT-3 Encoder Invalid2.3 100BASE-TX Transmit Framing Transmit DriverMagnetics Modules Vendor Model/Type3 100BASE-TX Receive Blocks 5 100BASE-TX Link Integrity and Auto-Negotiation Solution 10BASE-T Functionality4 100BASE-TX Collision Detection Auto 10/100 Mbps Speed Selection2 10BASE-T Transmit Blocks 3 10BASE-T Receive Blocks2.1 10BASE-T Manchester Encoder 2.2 10BASE-T Driver and FilterAuto-Negotiation Functionality 4 10BASE-T Collision Detection5 10BASE-T Link Integrity 6 10BASE-T Jabber Control FunctionDescription Parallel Detect and Auto-NegotiationLED Description Auto-Negotiation and Parallel DetectTwo and Three LED Schematic Diagram Liled T L E DPCI Vendor ID and Device ID Registers PCI Configuration RegistersLAN Ethernet PCI Configuration Space PCI Command Register PCI Command Register PCI Command Register BitsPCI Status Register PCI Status Register PCI Status Register BitsPCI Cache Line Size Register PCI Revision ID RegisterPCI Class Code Register PCI Base Address Registers PCI Latency TimerPCI Header Type CSR Memory Mapped Base Address Register CSR I/O Mapped Base Address RegisterFlash Memory Mapped Base Address Register Expansion ROM Base Address RegisterPCI Subsystem Vendor ID and Subsystem ID Registers Capability PointerInterrupt Line Register ER ID Fields ProgrammingPower Management Capabilities Register Interrupt Pin RegisterMinimum Grant Register Maximum Latency RegisterPower Management Control/Status Register Pmcsr Power Management Control and Status RegisterData Select Data Scale Data Reported Data RegisterEthernet Data Register Control/Status Registers LAN Ethernet Control/Status RegistersD31 D16 D15 Lower Word OffsetSystem Control Block Status Word System Control Block Command Word System Control Block General PointerPort Flash Control RegisterReceive Direct Memory Access Byte Count Power Management Driver RegisterPower Management Driver Register Early Receive InterruptGeneral Control Register General Status RegisterGeneral Control Register General Status RegisterCounter Description Statistical CountersER Statistical Counters Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet Bits Name Description Default PHY Unit RegistersMDI Registers 0 Register 0 Control Register Bit DefinitionsRegister 1 Status Register Bit Definitions Bits Name Description Default 150 Register 2 PHY Identifier Register Bit DefinitionsRegister 3 PHY Identifier Register Bit Definitions Value 0154HMDI Registers 8 MDI Register 16100BASE-TX 10BASE-TRegister 17 PHY Unit Special Control Bit Definitions Bits Register 22 Receive Symbol Error Counter Bit DefinitionsRegister 18 PHY Address Register Register 23 100BASE-TX Receive Premature End of Frame Error Counter Bit DefinitionsRegister 26 Equalizer Control and Status Bit Definitions Register 27 PHY Unit Special Control Bit DefinitionsGD82559ER Networking Silicon Datasheet Electrical and Timing Specifications DC SpecificationsGeneral DC Specifications PCI Interface DC SpecificationsBASE-TX Voltage/Current Characteristics Flash/EEPROM Interface DC SpecificationsLED Voltage/Current Characteristics VCC/2 BASE-T Voltage/Current CharacteristicsSymbol Parameter AC Specifications AC Specifications for PCI SignalingTiming Specifications Clocks SpecificationsPCI Clock Specifications 10.4.1.2 X1 SpecificationsMeasurement and Test Conditions Symbol PCI Level UnitsTiming Parameters Symbol Parameter Min Max Units PCI TimingsFlash Interface Timings PCI Timing ParametersFlash Timing Parameters Eeprom Interface Timings Eeprom Timing ParametersSymbol Parameter Condition Min Typ Max Units Symbol Parameter Min Typ MaxPHY Timings BASE-T NLP Timing ParametersSymbol Parameter Condition Min Typ Max Units T64 TDP/TDN Differential HLS Data 1400 Output Peak JitterGD82559ER Networking Silicon Datasheet Package and Pinout Information Package InformationPinout Information 12.2.1 GD82559ER Pin AssignmentsGD82559ER Pin Assignments Pin NameSTOP# INTA# DEVSEL# VCC VSS PERR# GNT# VCCFLA1 FLA012.2.2 GD82559ER Ball Grid Array Diagram GD82559ER Ball Grid Array Diagram

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
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