Intel GD82559ER manual General Control Register, General Status Register

Page 67

 

 

 

Networking Silicon — GD82559ER

 

 

Table 11. Power Management Driver Register

 

 

 

 

Bits

Default

Read/Write

Description

 

 

 

 

 

 

 

 

29

0b

Read/Clear

Interesting Packet. This bit is set when an “interesting” packet is

 

 

 

received. Interesting packets are defined by the 82559ER packet

 

 

 

filters. This bit is cleared by writing 1b to it.

 

 

 

 

28:26

000b

Read Only

Reserved. These bits are reserved and should be set to 000b.

 

 

 

 

25

0b

Read/Clear

Reserved. These bit is reserved and should be set to 0b.

 

 

 

 

24

0b

Read/Clear

PME Status. This bit is a reflection of the PME Status bit in the Power

 

 

 

Management Control/Status Register (PMCSR). It is set upon a wake-

 

 

 

up event and is independent of the PME Enable bit.

 

 

 

This bit is cleared by writing 1b to it. This also clears the PME Status

 

 

 

bit in the PMCSR and de-asserts the PME signal. I

 

 

 

 

Note: The PMDR is initialized at ALTRST# reset only.

8.1.12General Control Register

The General Control register is a byte register and is described below.

 

 

 

Table 12. General Control Register

 

 

 

 

Bits

Default

Read/Write

Description

 

 

 

 

 

 

 

 

7:2

000000b

Read Only

Reserved. These bits are reserved and should be set to 000000b.

 

 

 

 

1

0b

Read/Write

Deep Power-Down on Link Down Enable. If a 1b is written to this

 

 

 

field, the 82559ER may enter a deep power-down state (sub-3 mA) in

 

 

 

the D2 and D3 power states while the link is down.

 

 

 

In this state, the 82559ER does not keep link integrity. This state is not

 

 

 

supported for point-to-point connection of two end stations.

 

 

 

 

0

0b

Read/Write

Clockrun Signal Disable. If this bit is set to 1b, then the 82559ER will

 

 

 

always request the PCI clock signal. This mode can be used to

 

 

 

overcome potential receive overruns caused by Clockrun signal

 

 

 

latencies over 5 μs.

 

 

 

 

8.1.13General Status Register

The General Status register is a byte register which indicates the link status of the 82559ER.

 

 

 

Table 13. General Status Register

 

 

 

 

Bits

Default

Read/Write

Description

 

 

 

 

 

 

 

 

7:3

00000b

Read Only

Reserved. These bits are reserved and should be set to 00000b.

 

 

 

 

2

--

Read Only

Duplex Mode. This bit indicates the wire duplex mode: full duplex (1b)

 

 

 

or half duplex (0b).

 

 

 

 

1

--

Read Only

Speed. This bit indicates the wire speed: 100 Mbps (1b) or 10 Mbps

 

 

 

(0b).

 

 

 

 

0

0b

Read Only

Link Status Indication. This bit indicates the status of the link: valid

 

 

 

(1b) or invalid (0b).

 

 

 

 

Datasheet

61

Page 66 Page 68
Image 67
Page 66 Page 68
Contents GD82559ER Fast Ethernet PCI Controller Product FeaturesMar First release Revision DescriptionContents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet GD82559ER Overview IntroductionSuggested Reading GD82559ER Networkin g Silicon Datasheet Parallel Subsystem Overview GD82559ER Architectural OverviewGD82559ER Networkin g Silicon Fifo Subsystem Overview10/100 Mbps Physical Layer Unit 10/100 Mbps Serial CSMA/CD Unit OverviewGD82559ER Networkin g Silicon Datasheet Address and Data Signals Signal DescriptionsSignal Type Definitions PCI Bus Interface SignalsInterface Control Signals System and Power Management Signals Local Memory Interface SignalsTestability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet D3 to D0 Software Selective GD82559ER Media Access Control Functional Description82559ER Initialization Initialization Effects on 82559ER Units1.1 82559ER Bus Slave Operation Control/Status Register CSR AccessesPCI Interface 1 82559ER Bus OperationsCSR I/O Read Cycle Flash Buffer Read Cycle Flash Buffer AccessesFlash Buffer Write Cycle Retry Premature Accesses1.2 82559ER Bus Master Operation Error HandlingMemory Read Burst Cycle Memory Write and Invalidate Read Align Power Management Event Signal Clockrun Signal4.3 D2 Power State Power States4.1 D0 Power State 4.2 D1 Power StatePCI CLK 4.4 D3 Power StateUnderstanding Power Requirements Power State Conditions 100 Mbs 10 MbsPower State Link 82559ER Functionality Auxiliary Power SignalAlternate Reset Signal Isolate SignalIsolate Signal Behavior to PCI Power Good Signal PCI Reset SignalInterestin g Packet Events Wake-up EventsSerial Eeprom Interface Parallel Flash InterfaceLink Status Change Event Subsystem ID Word IA ByteALL 10/100 Mbps CSMA/CD UnitEeprom Words Field Descriptions Bits Name DescriptionLong Frame Reception Full DuplexFlow Control Address Filtering ModificationsMedia Independent Interface MII Management Interface Test Function Description Asynchronous Test ModeGD82559ER Test Port Functionality IntroductionChain Order TriStateNand Tree Nand Tree ChainsAD9 STOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5FLD6 FLD7GD82559ER Networkin g Silicon Datasheet 2 100BASE-TX Transmit Blocks GD82559ER Physical Layer Functional Description100BASE-TX PHY Unit 1 100BASE-TX Transmit Clock GenerationInvalid 2.2 100BASE-TX Scrambler and MLT-3 EncoderVendor Model/Type 2.3 100BASE-TX Transmit FramingTransmit Driver Magnetics Modules3 100BASE-TX Receive Blocks Auto 10/100 Mbps Speed Selection 5 100BASE-TX Link Integrity and Auto-Negotiation Solution10BASE-T Functionality 4 100BASE-TX Collision Detection2.2 10BASE-T Driver and Filter 2 10BASE-T Transmit Blocks3 10BASE-T Receive Blocks 2.1 10BASE-T Manchester Encoder6 10BASE-T Jabber Control Function Auto-Negotiation Functionality4 10BASE-T Collision Detection 5 10BASE-T Link IntegrityParallel Detect and Auto-Negotiation DescriptionAuto-Negotiation and Parallel Detect LED DescriptionLiled T L E D Two and Three LED Schematic DiagramLAN Ethernet PCI Configuration Space PCI Configuration RegistersPCI Vendor ID and Device ID Registers PCI Command Register PCI Command Register Bits PCI Command RegisterPCI Status Register PCI Status Register Bits PCI Status RegisterPCI Class Code Register PCI Revision ID RegisterPCI Cache Line Size Register PCI Header Type PCI Latency TimerPCI Base Address Registers Expansion ROM Base Address Register CSR Memory Mapped Base Address RegisterCSR I/O Mapped Base Address Register Flash Memory Mapped Base Address RegisterER ID Fields Programming PCI Subsystem Vendor ID and Subsystem ID RegistersCapability Pointer Interrupt Line RegisterMaximum Latency Register Power Management Capabilities RegisterInterrupt Pin Register Minimum Grant RegisterPower Management Control and Status Register Power Management Control/Status Register PmcsrEthernet Data Register Data RegisterData Select Data Scale Data Reported D16 D15 Lower Word Offset Control/Status RegistersLAN Ethernet Control/Status Registers D31System Control Block Status Word Flash Control Register System Control Block Command WordSystem Control Block General Pointer PortEarly Receive Interrupt Receive Direct Memory Access Byte CountPower Management Driver Register Power Management Driver RegisterGeneral Status Register General Control RegisterGeneral Status Register General Control RegisterER Statistical Counters Statistical CountersCounter Description Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet Register 0 Control Register Bit Definitions Bits Name Description DefaultPHY Unit Registers MDI Registers 0Register 1 Status Register Bit Definitions Value 0154H Bits Name Description Default 150Register 2 PHY Identifier Register Bit Definitions Register 3 PHY Identifier Register Bit Definitions10BASE-T MDI Registers 8MDI Register 16 100BASE-TXRegister 17 PHY Unit Special Control Bit Definitions Register 18 PHY Address Register Register 22 Receive Symbol Error Counter Bit DefinitionsBits Register 27 PHY Unit Special Control Bit Definitions Register 23 100BASE-TX Receive Premature End of Frame ErrorCounter Bit Definitions Register 26 Equalizer Control and Status Bit DefinitionsGD82559ER Networking Silicon Datasheet PCI Interface DC Specifications Electrical and Timing SpecificationsDC Specifications General DC SpecificationsLED Voltage/Current Characteristics Flash/EEPROM Interface DC SpecificationsBASE-TX Voltage/Current Characteristics Symbol Parameter BASE-T Voltage/Current CharacteristicsVCC/2 AC Specifications for PCI Signaling AC Specifications10.4.1.2 X1 Specifications Timing SpecificationsClocks Specifications PCI Clock SpecificationsTiming Parameters Symbol PCI Level UnitsMeasurement and Test Conditions PCI Timing Parameters Symbol Parameter Min Max UnitsPCI Timings Flash Interface TimingsFlash Timing Parameters Eeprom Timing Parameters Eeprom Interface TimingsBASE-T NLP Timing Parameters Symbol Parameter Condition Min Typ Max UnitsSymbol Parameter Min Typ Max PHY TimingsTDP/TDN Differential HLS Data 1400 Output Peak Jitter Symbol Parameter Condition Min Typ Max Units T64GD82559ER Networking Silicon Datasheet Package Information Package and Pinout InformationPin Name Pinout Information12.2.1 GD82559ER Pin Assignments GD82559ER Pin AssignmentsFLA0 STOP# INTA# DEVSEL# VCC VSSPERR# GNT# VCC FLA1GD82559ER Ball Grid Array Diagram 12.2.2 GD82559ER Ball Grid Array Diagram

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
Top Page Image Contents