Intel GD82559ER PCI Revision ID Register, PCI Class Code Register, PCI Cache Line Size Register

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GD82559ER — Networkin g Silicon

 

 

Table 6. PCI Status Register Bits

 

 

 

Bits

Name

Description

 

 

 

 

 

 

 

 

This bit indicates whether a parity error has been detected. This bit is set to

 

 

1b when the following three conditions are met:

 

 

1. The bus agent asserted PERR# itself or observed PERR# asserted.

24

Parity Error Detected

2. The agent setting the bit acted as the bus master for the operation in

which the error occurred.

 

 

 

 

3. The Parity Error Response bit in the command register (bit 6) is set.

 

 

In the 82559ER, the initial value of the Parity Error Detected bit is 0b. This

 

 

bit is set until cleared by writing a 1b.

 

 

 

 

 

This bit indicates a device’s ability to accept fast back-to-back transactions

23

Fast Back-to-Back

when the transactions are not to the same agent. A value of 0b disables

fast back-to-back ability. A value of 1b enables fast back-to-back ability. In

 

 

 

 

the 82559ER, this bit is read only and is set to 1b.

 

 

 

 

 

This bit indicates whether the 82559ER implements a list of new

 

 

capabilities such as PCI Power Management. A value of 0b means that this

20

Capabilities List

function does not implement the Capabilities List. If this bit is set to 1b, the

Cap_Ptr register provides an offset into the 82559ER PCI Configuration

 

 

 

 

space pointing to the location of the first item in the Capabilities List. This

 

 

bit is set only if the power management bit in the EEPROM is set.

 

 

 

19:16

Reserved

These bits are reserved and should be set to 0000b.

 

 

 

7.1.4PCI Revision ID Register

The Revision ID is an 8-bit read only register with a default value of 08h for the 82559ER. The three least significant bits of the Revision ID can be overridden by the ID and Revision ID fields in the EEPROM (Section 4.4, “Serial EEPROM Interface” on page 28 ).

7.1.5PCI Class Code Register

The Class Code register is read only and is used to identify the generic function of the device and, in some cases, specific register level programming interface. The register is broken into three byte size fields. The upper byte is a base class code and specifies the 82559ER as a network controller, 2H. The middle byte is a subclass code and specifies the 82559ER as an Ethernet controller, 0H.

The lower byte identifies a specific register level programming interface and the 82559ER always returns a 0h in this field.

7.1.6PCI Cache Line Size Register

In order for the 82559ER to support the Memory Write and Invalidate (MWI) command, the 82559ER must also support the Cache Line Size (CLS) register in PCI Configuration space. The register supports only cache line sizes of 8 and 16 Dwords. Any value other than 8 or 16 that is written to the register is ignored and the 82559ER does not use the MWI command. If a value other than 8 or 16 is written into the CLS register, the 82559ER returns all zeroes when the CLS register is read. The figure below illustrates the format of this register.

7

6

5

4

3

2

1

0

0

0

0

RW

RW

0

0

0

Figure 20. Cache Line Size Register

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Datasheet

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Contents Product Features GD82559ER Fast Ethernet PCI ControllerRevision Description Mar First releaseContents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet Suggested Reading IntroductionGD82559ER Overview GD82559ER Networkin g Silicon Datasheet GD82559ER Architectural Overview Parallel Subsystem OverviewFifo Subsystem Overview GD82559ER Networkin g Silicon10/100 Mbps Serial CSMA/CD Unit Overview 10/100 Mbps Physical Layer UnitGD82559ER Networkin g Silicon Datasheet Signal Descriptions Signal Type DefinitionsPCI Bus Interface Signals Address and Data SignalsInterface Control Signals Local Memory Interface Signals System and Power Management SignalsTestability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet GD82559ER Media Access Control Functional Description 82559ER InitializationInitialization Effects on 82559ER Units D3 to D0 Software SelectiveControl/Status Register CSR Accesses PCI Interface1 82559ER Bus Operations 1.1 82559ER Bus Slave OperationCSR I/O Read Cycle Flash Buffer Accesses Flash Buffer Read CycleRetry Premature Accesses Flash Buffer Write CycleError Handling 1.2 82559ER Bus Master OperationMemory Read Burst Cycle Memory Write and Invalidate Read Align Clockrun Signal Power Management Event SignalPower States 4.1 D0 Power State4.2 D1 Power State 4.3 D2 Power State4.4 D3 Power State Understanding Power RequirementsPower State Conditions 100 Mbs 10 Mbs PCI CLKAuxiliary Power Signal Alternate Reset SignalIsolate Signal Power State Link 82559ER FunctionalityPCI Reset Signal Isolate Signal Behavior to PCI Power Good SignalWake-up Events Interestin g Packet EventsLink Status Change Event Parallel Flash InterfaceSerial Eeprom Interface Word IA Byte Subsystem ID10/100 Mbps CSMA/CD Unit Eeprom Words Field DescriptionsBits Name Description ALLFull Duplex Flow ControlAddress Filtering Modifications Long Frame ReceptionMedia Independent Interface MII Management Interface Asynchronous Test Mode GD82559ER Test Port FunctionalityIntroduction Test Function DescriptionTriState Nand TreeNand Tree Chains Chain OrderSTOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5 FLD6FLD7 AD9GD82559ER Networkin g Silicon Datasheet GD82559ER Physical Layer Functional Description 100BASE-TX PHY Unit1 100BASE-TX Transmit Clock Generation 2 100BASE-TX Transmit Blocks2.2 100BASE-TX Scrambler and MLT-3 Encoder Invalid2.3 100BASE-TX Transmit Framing Transmit DriverMagnetics Modules Vendor Model/Type3 100BASE-TX Receive Blocks 5 100BASE-TX Link Integrity and Auto-Negotiation Solution 10BASE-T Functionality4 100BASE-TX Collision Detection Auto 10/100 Mbps Speed Selection2 10BASE-T Transmit Blocks 3 10BASE-T Receive Blocks2.1 10BASE-T Manchester Encoder 2.2 10BASE-T Driver and FilterAuto-Negotiation Functionality 4 10BASE-T Collision Detection5 10BASE-T Link Integrity 6 10BASE-T Jabber Control FunctionDescription Parallel Detect and Auto-NegotiationLED Description Auto-Negotiation and Parallel DetectTwo and Three LED Schematic Diagram Liled T L E DPCI Vendor ID and Device ID Registers PCI Configuration RegistersLAN Ethernet PCI Configuration Space PCI Command Register PCI Command Register PCI Command Register BitsPCI Status Register PCI Status Register PCI Status Register BitsPCI Cache Line Size Register PCI Revision ID RegisterPCI Class Code Register PCI Base Address Registers PCI Latency TimerPCI Header Type CSR Memory Mapped Base Address Register CSR I/O Mapped Base Address RegisterFlash Memory Mapped Base Address Register Expansion ROM Base Address RegisterPCI Subsystem Vendor ID and Subsystem ID Registers Capability PointerInterrupt Line Register ER ID Fields ProgrammingPower Management Capabilities Register Interrupt Pin RegisterMinimum Grant Register Maximum Latency RegisterPower Management Control/Status Register Pmcsr Power Management Control and Status RegisterData Select Data Scale Data Reported Data RegisterEthernet Data Register Control/Status Registers LAN Ethernet Control/Status RegistersD31 D16 D15 Lower Word OffsetSystem Control Block Status Word System Control Block Command Word System Control Block General PointerPort Flash Control RegisterReceive Direct Memory Access Byte Count Power Management Driver RegisterPower Management Driver Register Early Receive InterruptGeneral Control Register General Status RegisterGeneral Control Register General Status RegisterCounter Description Statistical CountersER Statistical Counters Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet Bits Name Description Default PHY Unit RegistersMDI Registers 0 Register 0 Control Register Bit DefinitionsRegister 1 Status Register Bit Definitions Bits Name Description Default 150 Register 2 PHY Identifier Register Bit DefinitionsRegister 3 PHY Identifier Register Bit Definitions Value 0154HMDI Registers 8 MDI Register 16100BASE-TX 10BASE-TRegister 17 PHY Unit Special Control Bit Definitions Bits Register 22 Receive Symbol Error Counter Bit DefinitionsRegister 18 PHY Address Register Register 23 100BASE-TX Receive Premature End of Frame Error Counter Bit DefinitionsRegister 26 Equalizer Control and Status Bit Definitions Register 27 PHY Unit Special Control Bit DefinitionsGD82559ER Networking Silicon Datasheet Electrical and Timing Specifications DC SpecificationsGeneral DC Specifications PCI Interface DC SpecificationsBASE-TX Voltage/Current Characteristics Flash/EEPROM Interface DC SpecificationsLED Voltage/Current Characteristics VCC/2 BASE-T Voltage/Current CharacteristicsSymbol Parameter AC Specifications AC Specifications for PCI SignalingTiming Specifications Clocks SpecificationsPCI Clock Specifications 10.4.1.2 X1 SpecificationsMeasurement and Test Conditions Symbol PCI Level UnitsTiming Parameters Symbol Parameter Min Max Units PCI TimingsFlash Interface Timings PCI Timing ParametersFlash Timing Parameters Eeprom Interface Timings Eeprom Timing ParametersSymbol Parameter Condition Min Typ Max Units Symbol Parameter Min Typ MaxPHY Timings BASE-T NLP Timing ParametersSymbol Parameter Condition Min Typ Max Units T64 TDP/TDN Differential HLS Data 1400 Output Peak JitterGD82559ER Networking Silicon Datasheet Package and Pinout Information Package InformationPinout Information 12.2.1 GD82559ER Pin AssignmentsGD82559ER Pin Assignments Pin NameSTOP# INTA# DEVSEL# VCC VSS PERR# GNT# VCCFLA1 FLA012.2.2 GD82559ER Ball Grid Array Diagram GD82559ER Ball Grid Array Diagram

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
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