Intel GD82559ER manual Local Memory Interface Signals, System and Power Management Signals

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Networking Silicon —GD82559ER

3.2.3System and Power Management Signals

Symbol

Type

Name and Function

 

 

 

 

 

 

 

 

Clock. The Clock signal provides the timing for all PCI transactions

 

 

and is an input signal to every PCI device. The 82559ER requires a

CLK

IN

PCI Clock signal (frequency greater than or equal to 16 MHz) for

 

 

nominal operation. The 82559ER supports Clock signal suspension

 

 

using the Clockrun protocol.

 

 

 

 

 

Clockrun. The Clockrun signal is used by the system to pause or slow

 

IN/OUT

down the PCI Clock signal. It is used by the 82559ER to enable or

CLKRUN#

disable suspension of the PCI Clock signal or restart of the PCI clock.

O/D

 

When the Clockrun signal is not used, this pin should be connected to

 

 

 

 

an external pull-down resistor.

 

 

 

 

 

Reset. The PCI Reset signal is used to place PCI registers,

RST#

IN

sequencers, and signals into a consistent state. When RST# is

 

 

asserted, all PCI output signals will be tri-stated.

 

 

 

 

 

Power Management Event. The Power Management Event signal

PME#

O/D

indicates that a power management event has occurred in a PCI bus

 

 

system.

 

 

 

 

 

Isolate. The Isolate signal is used to isolate the 82559ER from the

 

 

PCI bus. When Isolate is active (low), the 82559ER does not drive its

ISOLATE#

IN

PCI outputs (except PME#) or sample its PCI inputs (including CLK

and RST#). If the 82559ER is not powered by an auxiliary power

 

 

 

 

source, the ISOLATE# pin should be pulled high to the bus Vcc

 

 

through a 4.7K-62K resistor.

 

 

 

 

 

Alternate Reset. The Alternate Reset signal is used to reset the

ALTRST#

IN

82559ER on power-up. In systems that support an auxiliary power

supply, ALTRST# should be connected to a power-up detection circuit.

 

 

 

 

Otherwise, ALTRST# should be tied to Vcc.

 

 

Voltage Input/Output. The VIO pin is the a voltage bias pin for the

 

B

PCI interface. This pin should be connected to 5V ± 5% in a 5 volt PCI

VIO

system and 3.3 volts in a 3.3 volt PCI system. Be sure to install a 10K

IN

pull-up resistor. This resistor acts as a current limit resistor in system

 

 

 

where the VIO bias voltage maybe shutdown. In this cases the

 

 

82559ER may consume additional current without a resistor.

 

 

 

3.3Local Memory Interface Signals

Symbol

Type

Name and Function

 

 

 

 

 

 

FLD[7:0]

T/S

Flash Data Input/Output. These pins are used for Flash data

interface.

 

 

 

 

 

 

 

Flash Address[16]/25 MHz Clock. This multiplexed pin is controlled

FLA[16]/

OUT

by the status of the Flash Address[7] (FLA[7]) pin. If FLA[7] is left

CLK25

floating, this pin is used as FLA[16]; otherwise, if FLA[7] is connected

 

 

 

to a pull-up resistor, this pin is used as a 25 MHz clock.

 

 

 

 

 

Flash Address[15]/EEPROM Data Output. During Flash accesses,

FLA[15]/

OUT

this multiplexed pin acts as the Flash Address [15] output signal.

EESK

During EEPROM accesses, it acts as the serial shift clock output to

 

 

 

the EEPROM.

 

 

 

 

 

Flash Address[14]/EEPROM Data Output. During Flash accesses,

FLA[14]/

IN/OUT

this multiplexed pin acts as the Flash Address [14] output signal.

EEDO

During EEPROM accesses, it acts as serial input data to the EEPROM

 

 

 

Data Output signal.

 

 

 

Datasheet

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Contents GD82559ER Fast Ethernet PCI Controller Product FeaturesMar First release Revision DescriptionContents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet Introduction GD82559ER OverviewSuggested Reading GD82559ER Networkin g Silicon Datasheet Parallel Subsystem Overview GD82559ER Architectural OverviewGD82559ER Networkin g Silicon Fifo Subsystem Overview10/100 Mbps Physical Layer Unit 10/100 Mbps Serial CSMA/CD Unit OverviewGD82559ER Networkin g Silicon Datasheet Address and Data Signals Signal DescriptionsSignal Type Definitions PCI Bus Interface SignalsInterface Control Signals System and Power Management Signals Local Memory Interface SignalsTestability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet D3 to D0 Software Selective GD82559ER Media Access Control Functional Description82559ER Initialization Initialization Effects on 82559ER Units1.1 82559ER Bus Slave Operation Control/Status Register CSR AccessesPCI Interface 1 82559ER Bus OperationsCSR I/O Read Cycle Flash Buffer Read Cycle Flash Buffer AccessesFlash Buffer Write Cycle Retry Premature Accesses1.2 82559ER Bus Master Operation Error HandlingMemory Read Burst Cycle Memory Write and Invalidate Read Align Power Management Event Signal Clockrun Signal4.3 D2 Power State Power States4.1 D0 Power State 4.2 D1 Power StatePCI CLK 4.4 D3 Power StateUnderstanding Power Requirements Power State Conditions 100 Mbs 10 MbsPower State Link 82559ER Functionality Auxiliary Power SignalAlternate Reset Signal Isolate SignalIsolate Signal Behavior to PCI Power Good Signal PCI Reset SignalInterestin g Packet Events Wake-up EventsParallel Flash Interface Serial Eeprom InterfaceLink Status Change Event Subsystem ID Word IA ByteALL 10/100 Mbps CSMA/CD UnitEeprom Words Field Descriptions Bits Name DescriptionLong Frame Reception Full DuplexFlow Control Address Filtering ModificationsMedia Independent Interface MII Management Interface Test Function Description Asynchronous Test ModeGD82559ER Test Port Functionality IntroductionChain Order TriStateNand Tree Nand Tree ChainsAD9 STOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5FLD6 FLD7GD82559ER Networkin g Silicon Datasheet 2 100BASE-TX Transmit Blocks GD82559ER Physical Layer Functional Description100BASE-TX PHY Unit 1 100BASE-TX Transmit Clock GenerationInvalid 2.2 100BASE-TX Scrambler and MLT-3 EncoderVendor Model/Type 2.3 100BASE-TX Transmit FramingTransmit Driver Magnetics Modules3 100BASE-TX Receive Blocks Auto 10/100 Mbps Speed Selection 5 100BASE-TX Link Integrity and Auto-Negotiation Solution10BASE-T Functionality 4 100BASE-TX Collision Detection2.2 10BASE-T Driver and Filter 2 10BASE-T Transmit Blocks3 10BASE-T Receive Blocks 2.1 10BASE-T Manchester Encoder6 10BASE-T Jabber Control Function Auto-Negotiation Functionality4 10BASE-T Collision Detection 5 10BASE-T Link IntegrityParallel Detect and Auto-Negotiation DescriptionAuto-Negotiation and Parallel Detect LED DescriptionLiled T L E D Two and Three LED Schematic DiagramPCI Configuration Registers LAN Ethernet PCI Configuration SpacePCI Vendor ID and Device ID Registers PCI Command Register PCI Command Register Bits PCI Command RegisterPCI Status Register PCI Status Register Bits PCI Status RegisterPCI Revision ID Register PCI Class Code RegisterPCI Cache Line Size Register PCI Latency Timer PCI Header TypePCI Base Address Registers Expansion ROM Base Address Register CSR Memory Mapped Base Address RegisterCSR I/O Mapped Base Address Register Flash Memory Mapped Base Address RegisterER ID Fields Programming PCI Subsystem Vendor ID and Subsystem ID RegistersCapability Pointer Interrupt Line RegisterMaximum Latency Register Power Management Capabilities RegisterInterrupt Pin Register Minimum Grant RegisterPower Management Control and Status Register Power Management Control/Status Register PmcsrData Register Ethernet Data RegisterData Select Data Scale Data Reported D16 D15 Lower Word Offset Control/Status RegistersLAN Ethernet Control/Status Registers D31System Control Block Status Word Flash Control Register System Control Block Command WordSystem Control Block General Pointer PortEarly Receive Interrupt Receive Direct Memory Access Byte CountPower Management Driver Register Power Management Driver RegisterGeneral Status Register General Control RegisterGeneral Status Register General Control RegisterStatistical Counters ER Statistical CountersCounter Description Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet Register 0 Control Register Bit Definitions Bits Name Description DefaultPHY Unit Registers MDI Registers 0Register 1 Status Register Bit Definitions Value 0154H Bits Name Description Default 150Register 2 PHY Identifier Register Bit Definitions Register 3 PHY Identifier Register Bit Definitions10BASE-T MDI Registers 8MDI Register 16 100BASE-TXRegister 17 PHY Unit Special Control Bit Definitions Register 22 Receive Symbol Error Counter Bit Definitions Register 18 PHY Address RegisterBits Register 27 PHY Unit Special Control Bit Definitions Register 23 100BASE-TX Receive Premature End of Frame ErrorCounter Bit Definitions Register 26 Equalizer Control and Status Bit DefinitionsGD82559ER Networking Silicon Datasheet PCI Interface DC Specifications Electrical and Timing SpecificationsDC Specifications General DC SpecificationsFlash/EEPROM Interface DC Specifications LED Voltage/Current CharacteristicsBASE-TX Voltage/Current Characteristics BASE-T Voltage/Current Characteristics Symbol ParameterVCC/2 AC Specifications for PCI Signaling AC Specifications10.4.1.2 X1 Specifications Timing SpecificationsClocks Specifications PCI Clock SpecificationsSymbol PCI Level Units Timing ParametersMeasurement and Test Conditions PCI Timing Parameters Symbol Parameter Min Max UnitsPCI Timings Flash Interface TimingsFlash Timing Parameters Eeprom Timing Parameters Eeprom Interface TimingsBASE-T NLP Timing Parameters Symbol Parameter Condition Min Typ Max UnitsSymbol Parameter Min Typ Max PHY TimingsTDP/TDN Differential HLS Data 1400 Output Peak Jitter Symbol Parameter Condition Min Typ Max Units T64GD82559ER Networking Silicon Datasheet Package Information Package and Pinout InformationPin Name Pinout Information12.2.1 GD82559ER Pin Assignments GD82559ER Pin AssignmentsFLA0 STOP# INTA# DEVSEL# VCC VSSPERR# GNT# VCC FLA1GD82559ER Ball Grid Array Diagram 12.2.2 GD82559ER Ball Grid Array Diagram

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
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