Intel GD82559ER manual Interface Control Signals

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GD82559ER — Networkin g Silicon

3.2.2Interface Control Signals

Symbol

Type

Name and Function

 

 

 

 

 

 

 

 

Cycle Frame. The cycle frame signal is driven by the current master

FRAME#

S/T/S

to indicate the beginning and duration of a transaction. FRAME# is

asserted to indicate the start of a transaction and de-asserted during

 

 

 

 

the final data phase.

 

 

 

 

 

Initiator Ready. The initiator ready signal indicates the bus master’s

 

 

ability to complete the current data phase and is used in conjunction

IRDY#

S/T/S

with the target ready (TRDY#) signal. A data phase is completed on

 

 

any clock cycle where both IRDY# and TRDY# are sampled asserted

 

 

(low) simultaneously.

 

 

 

 

 

Target Ready. The target ready signal indicates the selected device’s

 

 

ability to complete the current data phase and is used in conjunction

TRDY#

S/T/S

with the initiator ready (IRDY#) signal. A data phase is completed on

 

 

any clock cycle where both IRDY# and TRDY# are sampled asserted

 

 

(low) simultaneously.

 

 

 

 

 

Stop. The stop signal is driven by the target to indicate to the initiator

 

 

that it wishes to stop the current transaction. As a bus slave, STOP# is

STOP#

S/T/S

driven by the 82559ER to inform the bus master to stop the current

 

 

transaction. As a bus master, STOP# is received by the 82559ER to

 

 

stop the current transaction.

 

 

 

 

 

Initialization Device Select. The initialization device select signal is

IDSEL

IN

used by the 82559ER as a chip select during PCI configuration read

and write transactions. This signal is provided by the host in PCI

 

 

 

 

systems.

 

 

 

 

 

Device Select. The device select signal is asserted by the target once

 

 

it has detected its address. As a bus master, the DEVSEL# is an input

DEVSEL#

S/T/S

signal to the 82559ER indicating whether any device on the bus has

been selected. As a bus slave, the 82559ER asserts DEVSEL# to

 

 

 

 

indicate that it has decoded its address as the target of the current

 

 

transaction.

 

 

 

 

 

Request. The request signal indicates to the bus arbiter that the

REQ#

T/S

82559ER desires use of the bus. This is a point-to-point signal and

 

 

every bus master has its own REQ#.

 

 

 

 

 

Grant. The grant signal is asserted by the bus arbiter and indicates to

GNT#

IN

the 82559ER that access to the bus has been granted. This is a point-

 

 

to-point signal and every master has its own GNT#.

 

 

 

INTA#

O/D

Interrupt A. The interrupt A signal is used to request an interrupt by

the 82559ER. This is an active low, level triggered interrupt signal.

 

 

 

 

 

SERR#

O/D

System Error. The system error signal is used to report address

parity errors. When an error is detected, SERR# is driven low for a

 

 

single PCI clock.

 

 

 

 

 

Parity Error. The parity error signal is used to report data parity errors

 

 

during all PCI transactions except a Special Cycle. The parity error pin

 

 

is asserted two clock cycles after the error was detected by the device

PERR#

S/T/S

receiving data. The minimum duration of PERR# is one clock for each

 

 

data phase where an error is detected. A device cannot report a parity

 

 

error until it has claimed the access by asserting DEVSEL# and

 

 

completed a data phase.

 

 

 

8

Datasheet

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Contents Product Features GD82559ER Fast Ethernet PCI ControllerRevision Description Mar First releaseContents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet Suggested Reading IntroductionGD82559ER Overview GD82559ER Networkin g Silicon Datasheet GD82559ER Architectural Overview Parallel Subsystem OverviewFifo Subsystem Overview GD82559ER Networkin g Silicon10/100 Mbps Serial CSMA/CD Unit Overview 10/100 Mbps Physical Layer UnitGD82559ER Networkin g Silicon Datasheet PCI Bus Interface Signals Signal DescriptionsSignal Type Definitions Address and Data SignalsInterface Control Signals Local Memory Interface Signals System and Power Management SignalsTestability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet Initialization Effects on 82559ER Units GD82559ER Media Access Control Functional Description82559ER Initialization D3 to D0 Software Selective1 82559ER Bus Operations Control/Status Register CSR AccessesPCI Interface 1.1 82559ER Bus Slave OperationCSR I/O Read Cycle Flash Buffer Accesses Flash Buffer Read CycleRetry Premature Accesses Flash Buffer Write CycleError Handling 1.2 82559ER Bus Master OperationMemory Read Burst Cycle Memory Write and Invalidate Read Align Clockrun Signal Power Management Event Signal4.2 D1 Power State Power States4.1 D0 Power State 4.3 D2 Power StatePower State Conditions 100 Mbs 10 Mbs 4.4 D3 Power StateUnderstanding Power Requirements PCI CLKIsolate Signal Auxiliary Power SignalAlternate Reset Signal Power State Link 82559ER FunctionalityPCI Reset Signal Isolate Signal Behavior to PCI Power Good SignalWake-up Events Interestin g Packet EventsLink Status Change Event Parallel Flash InterfaceSerial Eeprom Interface Word IA Byte Subsystem IDBits Name Description 10/100 Mbps CSMA/CD UnitEeprom Words Field Descriptions ALLAddress Filtering Modifications Full DuplexFlow Control Long Frame ReceptionMedia Independent Interface MII Management Interface Introduction Asynchronous Test ModeGD82559ER Test Port Functionality Test Function DescriptionNand Tree Chains TriStateNand Tree Chain OrderFLD7 STOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5FLD6 AD9GD82559ER Networkin g Silicon Datasheet 1 100BASE-TX Transmit Clock Generation GD82559ER Physical Layer Functional Description100BASE-TX PHY Unit 2 100BASE-TX Transmit Blocks2.2 100BASE-TX Scrambler and MLT-3 Encoder InvalidMagnetics Modules 2.3 100BASE-TX Transmit FramingTransmit Driver Vendor Model/Type3 100BASE-TX Receive Blocks 4 100BASE-TX Collision Detection 5 100BASE-TX Link Integrity and Auto-Negotiation Solution10BASE-T Functionality Auto 10/100 Mbps Speed Selection2.1 10BASE-T Manchester Encoder 2 10BASE-T Transmit Blocks3 10BASE-T Receive Blocks 2.2 10BASE-T Driver and Filter5 10BASE-T Link Integrity Auto-Negotiation Functionality4 10BASE-T Collision Detection 6 10BASE-T Jabber Control FunctionDescription Parallel Detect and Auto-NegotiationLED Description Auto-Negotiation and Parallel DetectTwo and Three LED Schematic Diagram Liled T L E DPCI Vendor ID and Device ID Registers PCI Configuration RegistersLAN Ethernet PCI Configuration Space PCI Command Register PCI Command Register PCI Command Register BitsPCI Status Register PCI Status Register PCI Status Register BitsPCI Cache Line Size Register PCI Revision ID RegisterPCI Class Code Register PCI Base Address Registers PCI Latency TimerPCI Header Type Flash Memory Mapped Base Address Register CSR Memory Mapped Base Address RegisterCSR I/O Mapped Base Address Register Expansion ROM Base Address RegisterInterrupt Line Register PCI Subsystem Vendor ID and Subsystem ID RegistersCapability Pointer ER ID Fields ProgrammingMinimum Grant Register Power Management Capabilities RegisterInterrupt Pin Register Maximum Latency RegisterPower Management Control/Status Register Pmcsr Power Management Control and Status RegisterData Select Data Scale Data Reported Data RegisterEthernet Data Register D31 Control/Status RegistersLAN Ethernet Control/Status Registers D16 D15 Lower Word OffsetSystem Control Block Status Word Port System Control Block Command WordSystem Control Block General Pointer Flash Control RegisterPower Management Driver Register Receive Direct Memory Access Byte CountPower Management Driver Register Early Receive InterruptGeneral Control Register General Control RegisterGeneral Status Register General Status RegisterCounter Description Statistical CountersER Statistical Counters Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet MDI Registers 0 Bits Name Description DefaultPHY Unit Registers Register 0 Control Register Bit DefinitionsRegister 1 Status Register Bit Definitions Register 3 PHY Identifier Register Bit Definitions Bits Name Description Default 150Register 2 PHY Identifier Register Bit Definitions Value 0154H100BASE-TX MDI Registers 8MDI Register 16 10BASE-TRegister 17 PHY Unit Special Control Bit Definitions Bits Register 22 Receive Symbol Error Counter Bit DefinitionsRegister 18 PHY Address Register Register 26 Equalizer Control and Status Bit Definitions Register 23 100BASE-TX Receive Premature End of Frame ErrorCounter Bit Definitions Register 27 PHY Unit Special Control Bit DefinitionsGD82559ER Networking Silicon Datasheet General DC Specifications Electrical and Timing SpecificationsDC Specifications PCI Interface DC SpecificationsBASE-TX Voltage/Current Characteristics Flash/EEPROM Interface DC SpecificationsLED Voltage/Current Characteristics VCC/2 BASE-T Voltage/Current CharacteristicsSymbol Parameter AC Specifications AC Specifications for PCI SignalingPCI Clock Specifications Timing SpecificationsClocks Specifications 10.4.1.2 X1 SpecificationsMeasurement and Test Conditions Symbol PCI Level UnitsTiming Parameters Flash Interface Timings Symbol Parameter Min Max UnitsPCI Timings PCI Timing ParametersFlash Timing Parameters Eeprom Interface Timings Eeprom Timing ParametersPHY Timings Symbol Parameter Condition Min Typ Max UnitsSymbol Parameter Min Typ Max BASE-T NLP Timing ParametersSymbol Parameter Condition Min Typ Max Units T64 TDP/TDN Differential HLS Data 1400 Output Peak JitterGD82559ER Networking Silicon Datasheet Package and Pinout Information Package InformationGD82559ER Pin Assignments Pinout Information12.2.1 GD82559ER Pin Assignments Pin NameFLA1 STOP# INTA# DEVSEL# VCC VSSPERR# GNT# VCC FLA012.2.2 GD82559ER Ball Grid Array Diagram GD82559ER Ball Grid Array Diagram

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
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