Emerson CC1000DM I. .B.U. S. . C. .O. N. .T.R. O. .L. .S.I.G. N. .A.L. S, PCI Bus Control Signals

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P M C / P C I I N T E R F A C E

PCI Bus Control Signals

Test Data Output signal acts as the output port for test data and test instructions out of the PMC slots during TAP operation.

TMS: Test Mode Select controls the state of the TAP controller in the PMC slots.

TDI: Test Data Input signal acts as the input port for test data and test instructions into the PMC slots during TAP operation.

.P.C.I. .B.U. S. . C. .O. N. .T.R. O. .L. .S.I.G. N. .A.L. S. . . . . . . . . . . . . . . . . . . . . . . . .

The following signals for the PCI interface are available on connectors J1x and J2x. Refer to the PCI specification for detailed usage on these signals. All signals are bi- directional unless otherwise stated.

ACK64*, REQ64*: ACKNOWLEDGE and REQUEST output signals are used to tell a 64-bit PCI device whether to use the 64-bit or the 32-bit data width.

AD00-AD63:ADDRESS and DATA bus (bits 0-63) tri-state lines are used for both address and data handling. A bus transaction consists of an address phase followed by one or more data phases.

C/BE0* - C/BE7*: BUS COMMAND and BYTE ENABLES tri-state lines have different functions depending on the phase of a transaction. During the address phase of a transaction these lines define the bus command. During a data phase the lines are used as byte enables.

CLK: CLOCK input signal to the PMC modules provides timing for PCI transactions.

DEVSEL*: DEVICE SELECT sustained tri-state signal indicates when a device on the bus has been selected as the target of the current access.

EREADY: ENUMERATION READY open-drain output signal of a non-Monarch PrPMC indicates it has completed its on-board initialization and can respond to PCI bus enumeration. As an input signal to the Monarch PrPMC, it indicates all non-Monarchs have completed their on-board initialization and can respond to PCI bus enumeration.

FRAME*: CYCLE FRAME sustained tri-state line is driven by the current master to indicate the beginning of an access, and continues to be asserted until the transaction reaches its final data phase.

GNT*: GRANT input signal indicates that access to the bus has been granted to a particular master. Each master has its own GNT*.

IDSEL: INITIALIZATION DEVICE SELECT input signal acts as a chip select during configuration read and write transactions.

IDSELB: INITIALIZATION DEVICE SELECT B; if the optional second PCI agent is implemented, then IDSELB is connected as its IDSEL input.

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Contents CC1000dm Revision Level Principal Changes Date Regulatory Agency Warnings & Notices EC Declaration of Conformity Contents PCI Bridge Features PMC Module Installation Bridge EepromFigures G u r e s Tables Ta b l e s Registers G i s t e r s Overview N. .C.T.I.O. N. .A. L. . O. .V.E. R. .V.I.E.W Functional OverviewRoHS Compliance Type SpecificationProduct Certification Terminology and Notation Technical ReferencesAdditional Information Device / Interface DocumentDocument 6CC1000dm User’s Manual 10004281-02 Setup Width DepthCC1000dm Circuit Board Component Map, Top revCC1000dm Circuit Board Identification Numbers Connectors Fuses and Jumpers Jumper/Header Locations, Top View CC1000dm Setup Multiple Option Selection JP3CC1000dm Setup Signal Name Bit SelectionSignal Name Pin SignalBit Selection Jumper Jumper Position ModeSelPower Requirements Environmental ConsiderationsOperational Checks Typical Current Voltage Range AmpsS. E. .T. .M. E. .T.H. O. .D.S Reset Methods Non-transparentTroubleshooting O. U. .B. L. E. .S.H. O. .O. T. I. N. .G14CC1000dm User’s Manual 10004281-02 PMC/PCI Interface PMC Module Installation Device MappingC / P C I I N T E R F a C E VoltsBase cPCI Interrupt Transparent Mode Assignment Secondary Timing InterruptsBase PCI Interrupt System controller modesInternal Arbiter Control Register CC1000dm Request/Grant Local PCI Bus Device I.D. G. .E. .E.E. P. .R.O. M Bridge EepromPCI 6254 Configuration Registers PCI 6254 Configuration Registers Power Management CSR38h Reserved Status Vendor Device Subsystem ID hex PCI 6254 Bridge ModePCI Identification Values PCI Bus Control Signals I. .B.U. S. . C. .O. N. .T.R. O. .L. .S.I.G. N. .A.L. SPCI Bus Control Signals PMC Connector Pin Assignments Pin J11 J12 J13 J14Pin J11 J13 J14 Pin J11 J12Pin J21 J23 J24 Pin J21 J22Pin J21 J22 J23 J24 Carrier Card BUS Interface O. C. .K. .G. E. .N. E. R. .A.T. I.O. .N Arbitration and Device SelectionHot Swap Model DescriptionImplementation Hot SwapPin Row Z Row a Row B Row C Row D Row E Row F CC1000dm Control SignalsSignal Description Backplane Connector Pin Assignments Pin Row Z Row a Row B Row C Row D Row ERow F Pin Row a Row B Row C Row D Row E Row FPin Row a Row B Row C Row D Row E Backplane Connector Pin Assignments 10CC1000dm User’s Manual 10004281-02 CPCI PrPMCO s s a r y Index D e Page W. a r t e s y n c p . c o m
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