Emerson CC1000DM user manual Timing Interrupts, Base PCI, Interrupt System controller modes

Page 35

Timing

Interrupts

Table 3-3:

PMCx Interrupt Mapping

P M C / P C I I N T E R F A C E

.

.

PMC Module Installation

.

 

 

. .

The module interface transfers data between the PCI and local memory at burst data rates. When two modules are installed, they both contend for ownership of a common bus, which may reduce the individual performance of each module. Specific transfer rates to the PCI bus are dependent on the module design.

Many PMC modules also incorporate a bridge chip between their PCI and local busses, essentially creating two bridges that must be crossed to complete a cycle. Often, the second bridge is a source of long delays due to the associated bus acquisition latency. Initialization and time-out values should be set up to accommodate any additional latency.

External interrupts that are controlled by the CC1000dm carrier card are routed to the on-board devices/slots as follows:

 

PMC1/ PMC2

PMC1

Base PCI

(Transparent, non-transparent, no

(Legacy mode only)

Interrupt

system controller modes)

Non-System Controller

Assignment (secondary):

System Controller PCI Interrupt Line:

PCI Interrupt Line:

 

 

 

INTA

INTA

(J21, pin 4)

INTC

(J11, pin 6)

 

 

 

 

 

 

INTB

 

INTB

(J21, pin 5)

INTD

(J11, pin 9)

 

 

 

 

 

 

INTC

PLX PCI 6254 (HB6)

INTC

(J21, pin 6)

INTA

(J11, pin 4)

 

 

 

 

 

INTD

INTD

(J21, pin 9)

INTB

(J11, pin 5)

 

 

 

 

 

 

Table 3-4:

cPCI Interrupt Mapping

Base cPCI Interrupt

 

Transparent Mode

 

 

Assignment:

 

(secondary):

 

Non-Transparent or Legacy Mode:

INTA

(J1, pin A3)

 

INTA

 

INTA (PCI 6254 primary side)

 

 

 

 

 

 

 

 

INTB

(J1, pin B3)

 

INTB

 

–

 

 

 

 

 

 

INTC

(J1, pin C3)

 

INTC

 

–

 

 

 

 

 

 

INTD

(J1, pin E3)

 

INTD

 

–

 

 

 

 

 

 

Arbitration The CC1000dm arbitration control for the on-board PCI devices is provided by the PLX PCI 6254 PCI-to-PCI bridge. The PCI 6254 arbitrates for use of the primary bus when initiating upstream transactions and for use of the secondary bus when forwarding downstream transactions. The primary bus arbiter is external to the PCI 6254, and the secondary bus is an internal arbiter on the PCI 6254.

10004281-02

CC1000dm User’s Manual 3-3

Page 34 Page 36
Image 35
Page 34 Page 36
Contents CC1000dm Revision Level Principal Changes Date Regulatory Agency Warnings & Notices EC Declaration of Conformity Contents Bridge Eeprom PCI Bridge Features PMC Module InstallationFigures G u r e s Tables Ta b l e s Registers G i s t e r s Overview Functional Overview N. .C.T.I.O. N. .A. L. . O. .V.E. R. .V.I.E.WRoHS Compliance Type SpecificationProduct Certification Device / Interface Document Terminology and NotationTechnical References Additional InformationDocument 6CC1000dm User’s Manual 10004281-02 Width Depth SetupComponent Map, Top rev CC1000dm Circuit BoardCC1000dm Circuit Board Identification Numbers Connectors Fuses and Jumpers Jumper/Header Locations, Top View Multiple Option Selection JP3 CC1000dm SetupSignal Name Bit Selection CC1000dm SetupJumper Position ModeSel Signal NamePin Signal Bit Selection JumperTypical Current Voltage Range Amps Power RequirementsEnvironmental Considerations Operational ChecksS. E. .T. .M. E. .T.H. O. .D.S Non-transparent Reset MethodsO. U. .B. L. E. .S.H. O. .O. T. I. N. .G Troubleshooting14CC1000dm User’s Manual 10004281-02 PMC/PCI Interface Volts PMC Module InstallationDevice Mapping C / P C I I N T E R F a C EInterrupt System controller modes Base cPCI Interrupt Transparent Mode Assignment SecondaryTiming Interrupts Base PCIInternal Arbiter Control Register CC1000dm Request/Grant Local PCI Bus Device Bridge Eeprom I.D. G. .E. .E.E. P. .R.O. MPCI 6254 Configuration Registers Power Management CSR PCI 6254 Configuration Registers38h Reserved Status Vendor Device Subsystem ID hex PCI 6254 Bridge ModePCI Identification Values I. .B.U. S. . C. .O. N. .T.R. O. .L. .S.I.G. N. .A.L. S PCI Bus Control SignalsPCI Bus Control Signals Pin J11 J12 J13 J14 PMC Connector Pin AssignmentsJ23 J24 Pin J21 J22 Pin J11J13 J14 Pin J11 J12 Pin J21Pin J21 J22 J23 J24 Carrier Card BUS Interface Arbitration and Device Selection O. C. .K. .G. E. .N. E. R. .A.T. I.O. .NModel Description Hot SwapHot Swap ImplementationPin Row Z Row a Row B Row C Row D Row E Row F CC1000dm Control SignalsSignal Description Pin Row Z Row a Row B Row C Row D Row E Backplane Connector Pin AssignmentsPin Row a Row B Row C Row D Row E Row F Row FPin Row a Row B Row C Row D Row E Backplane Connector Pin Assignments 10CC1000dm User’s Manual 10004281-02 PrPMC CPCIO s s a r y Index D e Page W. a r t e s y n c p . c o m
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