Emerson CC1000DM user manual PCI Bus Control Signals

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P M C / P C I I N T E R F A C E

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.

PCI Bus Control Signals

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. .

INTA*, INTB*, INTC*, INTD*:

PMC INTERRUPTS A, B, C, D lines are used to interrupt the CPU.

IRDY*:

INITIATOR READY sustained tri-state signal indicates that the bus master is ready to

 

complete the data phase of the transaction.

LOCK*:

LOCK sustained tri-state signal indicates an atomic operation to a bridge that may

 

require multiple transactions to complete.

M66EN:

66 MHZ ENABLE input pin indicates to a device whether the bus segment is operating

 

at 66 or 33 MHz.

MONARCH:

MONARCH when grounded, indicates that the PrPMC module is a Monarch and must

 

provide PCI bus enumeration and interrupt handling.

PAR:

PARITY is even parity across AD00-AD31 and C/BE0-C/BE3*. Parity generation is

 

required by all PCI agents. This tri-state signal is stable and valid one clock after the

 

address phase, and one clock after the bus master indicates that it is ready to complete

 

the data phase (either IRDY* or TRDY* is asserted). Once PAR is asserted, it remains

 

valid until one clock after the completion of the current data phase.

PAR64:

PARITY UPPER DWORD tri-state signal is even parity that protects AD[63:0] and

 

C/BE[7:0]*. PAR64 must be valid one clock after each address phase on any transaction

 

in which REQ64* is asserted.

PERR*:

PARITY ERROR sustained tri-state line is used to report parity errors during all PCI

 

transactions.

PME*:

Power Management Event optional open-drain signal (pull-up resistor required) allows

 

a device to request a change in the power state. Devices must be enabled by software

 

before asserting this signal.

REQ*:

REQUEST output pin indicates to the arbiter that a particular master wants to use the

 

bus.

RST*:

RESET; assertion of this input line brings PCI registers, sequencers, and signals to a

 

consistent state.

SERR*:

SYSTEMS ERROR open-collector output signal is used to report any system error with

 

catastrophic results.

STOP*:

STOP is a sustained tri-state signal used by the current target to request that the bus

 

master stop the current transaction.

TDI*:

TEST DATA INPUT signal serially shifts test data and test instructions into the device

 

during test access port (TAP) operation.

TDO*:

TEST DATA OUTPUT signal serially shifts test data and test instructions out of the

 

device during TAP operation.

TMS*:

TEST MODE SELECT input signal controls the state of the TAP controller in the device.

10004281-02

CC1000dm User’s Manual 3-13

Page 44 Page 46
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Page 44 Page 46
Contents CC1000dm Revision Level Principal Changes Date Regulatory Agency Warnings & Notices EC Declaration of Conformity Contents Bridge Eeprom PCI Bridge Features PMC Module InstallationFigures G u r e s Tables Ta b l e s Registers G i s t e r s Overview Functional Overview N. .C.T.I.O. N. .A. L. . O. .V.E. R. .V.I.E.WType Specification Product CertificationRoHS Compliance Technical References Terminology and NotationAdditional Information Device / Interface DocumentDocument 6CC1000dm User’s Manual 10004281-02 Width Depth SetupComponent Map, Top rev CC1000dm Circuit BoardCC1000dm Circuit Board Identification Numbers Connectors Fuses and Jumpers Jumper/Header Locations, Top View Multiple Option Selection JP3 CC1000dm SetupSignal Name Bit Selection CC1000dm SetupPin Signal Signal NameBit Selection Jumper Jumper Position ModeSelEnvironmental Considerations Power RequirementsOperational Checks Typical Current Voltage Range AmpsS. E. .T. .M. E. .T.H. O. .D.S Non-transparent Reset MethodsO. U. .B. L. E. .S.H. O. .O. T. I. N. .G Troubleshooting14CC1000dm User’s Manual 10004281-02 PMC/PCI Interface Device Mapping PMC Module InstallationC / P C I I N T E R F a C E VoltsTiming Interrupts Base cPCI Interrupt Transparent Mode Assignment SecondaryBase PCI Interrupt System controller modesInternal Arbiter Control Register CC1000dm Request/Grant Local PCI Bus Device Bridge Eeprom I.D. G. .E. .E.E. P. .R.O. MPCI 6254 Configuration Registers Power Management CSR PCI 6254 Configuration Registers38h Reserved Status PCI 6254 Bridge Mode PCI Identification ValuesVendor Device Subsystem ID hex I. .B.U. S. . C. .O. N. .T.R. O. .L. .S.I.G. N. .A.L. S PCI Bus Control SignalsPCI Bus Control Signals Pin J11 J12 J13 J14 PMC Connector Pin AssignmentsJ13 J14 Pin J11 J12 Pin J11Pin J21 J23 J24 Pin J21 J22Pin J21 J22 J23 J24 Carrier Card BUS Interface Arbitration and Device Selection O. C. .K. .G. E. .N. E. R. .A.T. I.O. .NModel Description Hot SwapHot Swap ImplementationCC1000dm Control Signals Signal DescriptionPin Row Z Row a Row B Row C Row D Row E Row F Pin Row Z Row a Row B Row C Row D Row E Backplane Connector Pin AssignmentsPin Row a Row B Row C Row D Row E Row F Row FPin Row a Row B Row C Row D Row E Backplane Connector Pin Assignments 10CC1000dm User’s Manual 10004281-02 PrPMC CPCIO s s a r y Index D e Page W. a r t e s y n c p . c o m
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