Ampro Corporation 5001692A manual CompactFlash Socket J12

Page 35

Chapter 3

Hardware

CompactFlash Socket (J12)

The board contains a Type II PC card connector, which allows for the insertion of a CompactFlash card. The CompactFlash card acts as a standard IDE Drive and is connected as [CF on Sec Master] in BIOS.

 

NOTE

 

Supports True IDE Mode and Type 1 or Type II PC cards in the

 

 

 

 

 

CompactFlash socket (J12).

 

 

 

 

 

 

 

Table 3-10. CompactFlash Interface Pin/Signal Descriptions (J12)

 

 

 

 

 

 

 

 

Pin #

Signal

 

Description

 

 

 

 

 

 

1

GND

 

Digital Ground

 

 

 

 

 

 

2

D3

 

Disk Data 3 – These signals (D0-D15) carry the Data, Commands, and Status

 

 

 

 

 

between the host and the controller. D0 is the LSB of the even Byte of the Word.

 

 

 

 

 

D8 is the LSB of the Odd Byte of the Word. All Task File operations occur in

 

 

 

 

 

byte mode on the low order bus D0-D7, while all data transfers are 16 bit using

 

 

 

 

 

D0-D15 provide the disk data signals.

 

3

D4

 

Disk Data 4 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

4

D5

 

Disk Data 5 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

5

D6

 

Disk Data 6 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

6

D7

 

Disk Data 7 – Refer to pin 2, D3, for more information.

 

 

 

 

 

 

7

CE1*

 

Card Enable 1 – This signal, along with CE2*, is used to select the card and

 

 

 

 

 

indicate to the card when a byte or word operation is being performed. This signal

 

 

 

 

 

accesses the even byte or odd byte of the word depending on A0 and CE2*.

 

8

GND

 

Digital Ground

 

 

 

 

 

 

9

GND

 

Digital Ground

 

 

 

 

 

 

10

GND

 

Digital Ground

 

 

 

 

 

 

11

GND

 

Digital Ground

 

 

 

 

 

 

12

GND

 

Digital Ground

 

 

 

 

 

 

13

Vcc

 

+5 volts ±5% power supply

 

 

 

 

 

 

14

GND

 

Digital Ground

 

 

 

 

 

 

15

GND

 

Digital Ground

 

 

 

 

 

 

16

GND

 

Digital Ground

 

 

 

 

 

 

17

GND

 

Digital Ground

 

 

 

 

 

 

18

A2

 

Address Select 2 – One of three signals (0 – 2) used to select one of eight

 

 

 

 

 

registers in the Task File. The host grounds all remaining address lines.

 

19

A1

 

Address Select 1 – Refer to A2 on pin-18 for more information.

 

 

 

 

 

 

20

A0

 

Address Select 0 – Refer to A2 on pin-18 for more information.

 

 

 

 

 

 

21

D0

 

Disk Data 0 – Refer to D3 on pin-2 for more information.

 

 

 

 

 

 

22

D1

 

Disk Data 1 – Refer to D3 on pin-2 for more information.

 

 

 

 

 

 

23

D2

 

Disk Data 2 – Refer to D3 on pin-2 for more information.

 

 

 

 

 

 

 

CoreModule 420

Reference Manual

29

Image 35
Contents CoreModule PC/104 Single Board Computer Reference Manual Audience Assumptions Contents Appendix a Table A-1 Reference Manual CoreModule Purpose of this Manual SpecificationsChip Specifications About This ManualOther Ampro Products Related Ampro ProductsCoreModule 420 Support Products Other CoreModule ProductsChapter Reference Manual CoreModule PC/104 Architecture Product OverviewCPU Module FeaturesProduct Description Chapter CRT Bios Block DiagramAtlas Major Integrated Circuits ICsChip Type Mfg Model Description Function StpcIDE Connectors, Jumpers, and LEDsConnector Definitions Jack/Plug # Access DescriptionLED Definitions Jumper # Installed RemovedIndicator Definition Jumper DefinitionsJP6 JP9 JP7 JP8 JP5 JP4 JP1 Dimension SpecificationsPhysical Specifications Mechanical SpecificationsThermal/Cooling Requirements Power SpecificationsEnvironmental Specifications Reference Manual Overview HardwareMemory CPU U14Use Address Size Memory hole size selected Address Map Interrupt Channel AssignmentsEC00-EC0F 0CFC-0CFFPC/104 Bus Interface P1A,B,C,D Pin # Signal Description P1 Row aPin # Signal Description P1 Row B Pin # Signal Description P1 Row C Pin # Signal Description P1 Row D DRQ7 DRQ5 DRQ6 Pdrq Pin # Signal DescriptionReset IDE Interface J6IDEPCS1 PiorPdack PirqCompactFlash Socket J12 ACT RDYIordy REGParallel Port Floppy/Parallel Port J4Floppy Disk Drive Port Rdata SlinStep PD3Serial 1 to RS485 Conversion Serial Ports J3, J9, J13, J14Pin # Signal DB9 # Description Usbpp USB Port J10Usbpwr UsbpnUtility Interface J5 RX+ Ethernet Interface J2TX+ Video LCD/CRT Interface J11 FP2 TftdclkTftde TftlpReal Time Clock RTC User Gpio SignalsMiscellaneous Serial Console Oops! Jumper Bios RecoverySerial Console Bios Setup Watchdog TimerPin # Signal Power Interface J7Pin Signal Descriptions Reference Manual CoreModule Introduction Bios SetupAccessing Bios Setup VGA Display Bios Setup Menu Item/Topic Accessing Bios Setup Serial ConsoleBios Setup Opening Screen Main Bios Setup MenuCdrom Bios Configuration ScreenChapter Bios Setup Chapter Bios Setup Chapter Bios Setup USB IRQ none, 1, 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or Converting the Splash Screen File Splash Screen CustomizationSplash Screen Image Requirements \splashconvert convert.idf Building the Example On-Board Flash Access and UseFlash Programming Requirements Example Assumptions Installing the Example ApplicationFlash Boot API Method Contact Information Appendix a Technical SupportAppendix a 2PH2R44SGA Appendix B Connector Part NumbersTeka GpioAppendix B Index See also Oops! jumper Bios SetupPost 64MB SdramSerial terminal ANSI-compatible Reference Manual CoreModule