Ampro Corporation 5001692A manual Miscellaneous, Real Time Clock RTC, User Gpio Signals

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Chapter 3

 

Hardware

 

 

 

 

 

Pin #

Signal

Description

 

38

VSYNC

Vertical Sync – This signal is used for the digital vertical sync output to the

 

 

 

CRT. Also used (with HSYNC) to signal power management state information

 

 

 

to the CRT per the VESA DPMS standard.

 

39

AGNDR

Analog Ground for Red

 

40

RED

Red – This pin provides the Red analog output to the CRT.

 

 

 

 

 

41

AGNDG

Analog Ground for Green

 

42

GREEN

Green – This pin provides the Green analog output to the CRT.

 

 

 

 

 

43

AGNDB

Analog Ground for Blue

 

44

BLUE

Blue – This pin provides the Blue analog output to the CRT.

 

 

 

 

Notes: The shaded area denotes power or ground. The signals marked with * indicate active low.

Miscellaneous

Real Time Clock (RTC)

The CoreModule 420 contains a Real Time (time of day) Clock (RTC), which can be backed up with a Lithium Battery. The CoreModule 420 will function without a battery in those environments, which prohibit inclusion of batteries. The CoreModule 420 will also continue to operate after the battery life has been exceeded. Under these conditions all setup information is restored from the onboard Flash memory during POST along with the default date and time information.

NOTE

Some operating systems require a valid default date and time to function.

 

 

User GPIO Signals

The CoreModule 420 provides GPIO pins for customer use and the signals are routed to connector J8. An example of how to use the GPIO pins is provided in the Miscellaneous Source Code Examples subdirectory, under the CoreModule 420 Software menu on the CoreModule 420 Doc & SW CD-ROM (cm420\software\examples\GPIO).

CAUTION To prevent a system crash, or render the CoreModule 420 BIOS unusable, do not attempt to use the master GPIO pins (GPIOs 0-7). The STPC Atlas processor has two GPIO blocks, master and slave. The slave GPIO pins are reserved for customer applications. The master GPIO pins are dedicated for BIOS use to control on-board peripherals. The master GPIO pins can not be used for customer applications.

The example program can be built by using the make.bat file. This produces a 16-bit DOS executable application, gpio.exe, which can be run on the CoreModule 420 to demonstrate the use of GPIO pins. For more information about the GPIO pin operation, refer to the Programming Manual for the STPC Atlas processor at:

http://www.stmcu.com/devicedocs-Atlas-75.html

40

Reference Manual

CoreModule 420

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Contents CoreModule PC/104 Single Board Computer Reference Manual Audience Assumptions Contents Appendix a Table A-1 Reference Manual CoreModule About This Manual SpecificationsChip Specifications Purpose of this ManualOther CoreModule Products Related Ampro ProductsCoreModule 420 Support Products Other Ampro ProductsChapter Reference Manual CoreModule Product Overview PC/104 ArchitectureProduct Description Module FeaturesCPU Chapter CRT Block Diagram BiosStpc Major Integrated Circuits ICsChip Type Mfg Model Description Function AtlasJack/Plug # Access Description Connectors, Jumpers, and LEDsConnector Definitions IDEJumper Definitions Jumper # Installed RemovedIndicator Definition LED DefinitionsJP6 JP9 JP7 JP8 JP5 JP4 JP1 Mechanical Specifications SpecificationsPhysical Specifications DimensionEnvironmental Specifications Power SpecificationsThermal/Cooling Requirements Reference Manual Hardware OverviewCPU U14 MemoryUse Address Size Memory hole size selected Interrupt Channel Assignments Address Map0CFC-0CFF EC00-EC0FPin # Signal Description P1 Row a PC/104 Bus Interface P1A,B,C,DPin # Signal Description P1 Row B Pin # Signal Description P1 Row C Pin # Signal Description P1 Row D DRQ6 DRQ5DRQ7 IDE Interface J6 Pin # Signal DescriptionReset PdrqPirq PiorPdack IDEPCS1CompactFlash Socket J12 REG RDYIordy ACTFloppy Disk Drive Port Floppy/Parallel Port J4Parallel Port PD3 SlinStep RdataSerial Ports J3, J9, J13, J14 Serial 1 to RS485 ConversionPin # Signal DB9 # Description Usbpn USB Port J10Usbpwr UsbppUtility Interface J5 TX+ Ethernet Interface J2RX+ Video LCD/CRT Interface J11 Tftlp TftdclkTftde FP2Miscellaneous User Gpio SignalsReal Time Clock RTC Oops! Jumper Bios Recovery Serial ConsoleWatchdog Timer Serial Console Bios SetupPin Signal Descriptions Power Interface J7Pin # Signal Reference Manual CoreModule Accessing Bios Setup VGA Display Bios SetupIntroduction Accessing Bios Setup Serial Console Bios Setup Menu Item/TopicMain Bios Setup Menu Bios Setup Opening ScreenBios Configuration Screen CdromChapter Bios Setup Chapter Bios Setup Chapter Bios Setup USB IRQ none, 1, 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or Splash Screen Image Requirements Splash Screen CustomizationConverting the Splash Screen File \splashconvert convert.idf Flash Programming Requirements On-Board Flash Access and UseBuilding the Example Flash Boot API Installing the Example ApplicationExample Assumptions Appendix a Technical Support Method Contact InformationAppendix a Gpio Appendix B Connector Part NumbersTeka 2PH2R44SGAAppendix B See also Oops! jumper Bios Setup Index64MB Sdram PostSerial terminal ANSI-compatible Reference Manual CoreModule