Chapter 3 | Hardware |
Ethernet Interface (J2)
The Ethernet solution is provided by the Intel 82551ER PCI controller chip and consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution. The 82551ER is a
•Full duplex or
•Full duplex support at 10Mbps or 100Mbps
•In full duplex mode the 82551ER adheres to the IEEE 802.3x Flow Control specification.
•In
•IEEE 802.3 10/100BaseT compatible physical layer to wire transformer
•Two on board LEDs support the speed and the link and activity status
•10BaseT
•Data transmission with minimum interframe spacing (IFS).
•IEEE 802.3x
•3kB transmit and 3kB receive FIFOs (helps prevent data underflow and overflow)
•IEEE 802.3x 100BaseTX flow control support
Table
Table
Pin # | Signal | Description | |
1 | TX+ | Analog Twisted Pair Ethernet Transmit Differential Pair – These pins transmit the | |
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| serial bit stream through the isolation transformer on the Unshielded Twisted Pair | |
2 | TX- | ||
Cable (UTP). | |||
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3 | RX+ | Analog Twisted Pair Ethernet Receive Differential Pair – These pins receive the | |
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| serial bit stream through the isolation transformer. | |
6 | RX- | ||
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4 | NU | Not Used (RJ45 termination) | |
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5 | NU | Not Used (RJ45 termination) | |
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7 | NU | Not Used (RJ45 termination) | |
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8 | NU | Not Used (RJ45 termination) | |
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Note: NU = Not Used.
CoreModule 420 | Reference Manual | 37 |