Ampro Corporation 5001692A manual Ethernet Interface J2, Tx+, Rx+

Page 43

Chapter 3

Hardware

Ethernet Interface (J2)

The Ethernet solution is provided by the Intel 82551ER PCI controller chip and consists of both the Media Access Controller (MAC) and the physical layer (PHY) combined into a single component solution. The 82551ER is a 32-bit PCI controller that features enhanced scatter-gather bus mastering capabilities, which enables the 82551ER to perform high-speed data transfers over the internal PCI bus. The 82551ER bus master capabilities enable the component to process high-level commands and perform multiple operations, thereby off-loading communication tasks from the system CPU. The Ethernet interface offers the following features:

Full duplex or half-duplex support

Full duplex support at 10Mbps or 100Mbps

In full duplex mode the 82551ER adheres to the IEEE 802.3x Flow Control specification.

In half-duplex mode, performance is enhanced by a proprietary collision reduction mechanism.

IEEE 802.3 10/100BaseT compatible physical layer to wire transformer

Two on board LEDs support the speed and the link and activity status

10BaseT auto-polarity correction

Data transmission with minimum interframe spacing (IFS).

IEEE 802.3x auto-negotiation support for speed and duplex operation

3kB transmit and 3kB receive FIFOs (helps prevent data underflow and overflow)

IEEE 802.3x 100BaseTX flow control support

Table 3-16 describes the pin-outs of the Ethernet connector J2.

Table 3-16. Ethernet Interface Pin/Signal Descriptions (J2)

Pin #

Signal

Description

1

TX+

Analog Twisted Pair Ethernet Transmit Differential Pair – These pins transmit the

 

 

serial bit stream through the isolation transformer on the Unshielded Twisted Pair

2

TX-

Cable (UTP).

 

 

 

 

 

3

RX+

Analog Twisted Pair Ethernet Receive Differential Pair – These pins receive the

 

 

serial bit stream through the isolation transformer.

6

RX-

 

 

 

 

4

NU

Not Used (RJ45 termination)

 

 

 

5

NU

Not Used (RJ45 termination)

 

 

 

7

NU

Not Used (RJ45 termination)

 

 

 

8

NU

Not Used (RJ45 termination)

 

 

 

Note: NU = Not Used.

CoreModule 420

Reference Manual

37

Image 43
Contents CoreModule PC/104 Single Board Computer Reference Manual Audience Assumptions Contents Appendix a Table A-1 Reference Manual CoreModule Purpose of this Manual SpecificationsChip Specifications About This ManualOther Ampro Products Related Ampro ProductsCoreModule 420 Support Products Other CoreModule ProductsChapter Reference Manual CoreModule PC/104 Architecture Product OverviewProduct Description Module FeaturesCPU Chapter CRT Bios Block DiagramAtlas Major Integrated Circuits ICsChip Type Mfg Model Description Function StpcIDE Connectors, Jumpers, and LEDsConnector Definitions Jack/Plug # Access DescriptionLED Definitions Jumper # Installed RemovedIndicator Definition Jumper DefinitionsJP6 JP9 JP7 JP8 JP5 JP4 JP1 Dimension SpecificationsPhysical Specifications Mechanical SpecificationsEnvironmental Specifications Power SpecificationsThermal/Cooling Requirements Reference Manual Overview HardwareMemory CPU U14Use Address Size Memory hole size selected Address Map Interrupt Channel AssignmentsEC00-EC0F 0CFC-0CFFPC/104 Bus Interface P1A,B,C,D Pin # Signal Description P1 Row aPin # Signal Description P1 Row B Pin # Signal Description P1 Row C Pin # Signal Description P1 Row D DRQ6 DRQ5DRQ7 Pdrq Pin # Signal DescriptionReset IDE Interface J6IDEPCS1 PiorPdack PirqCompactFlash Socket J12 ACT RDYIordy REGFloppy Disk Drive Port Floppy/Parallel Port J4Parallel Port Rdata SlinStep PD3Serial 1 to RS485 Conversion Serial Ports J3, J9, J13, J14Pin # Signal DB9 # Description Usbpp USB Port J10Usbpwr UsbpnUtility Interface J5 TX+ Ethernet Interface J2RX+ Video LCD/CRT Interface J11 FP2 TftdclkTftde TftlpMiscellaneous User Gpio SignalsReal Time Clock RTC Serial Console Oops! Jumper Bios RecoverySerial Console Bios Setup Watchdog TimerPin Signal Descriptions Power Interface J7Pin # Signal Reference Manual CoreModule Accessing Bios Setup VGA Display Bios SetupIntroduction Bios Setup Menu Item/Topic Accessing Bios Setup Serial ConsoleBios Setup Opening Screen Main Bios Setup MenuCdrom Bios Configuration ScreenChapter Bios Setup Chapter Bios Setup Chapter Bios Setup USB IRQ none, 1, 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or Splash Screen Image Requirements Splash Screen CustomizationConverting the Splash Screen File \splashconvert convert.idf Flash Programming Requirements On-Board Flash Access and UseBuilding the Example Flash Boot API Installing the Example ApplicationExample Assumptions Method Contact Information Appendix a Technical SupportAppendix a 2PH2R44SGA Appendix B Connector Part NumbersTeka GpioAppendix B Index See also Oops! jumper Bios SetupPost 64MB SdramSerial terminal ANSI-compatible Reference Manual CoreModule